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ADVANCED AND EVER ADVANCING
MITSUBISHI ELECTRIC
MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER 4500 SERIES
4551
Group
User's Manual
MITSUBISHI ELECTRIC
keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Preface
This user's manual describes the hardware and instructions of Mitsubishi's 4551 Group CMOS 4-bit microcomputer. After reading this manual, the user should have a through knowledge of the functions and features of the 4551 Group and should be able to fully utilize the product. The manual starts with specifications and ends with application examples.
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q CHAPTER 3 APPENDIX This chapter includes precautions for systems development using the microcomputer, the mask ROM confirmation forms (mask ROM version), ROM programming confirmation forms (One Time PROM version) and mark specification forms which are to be submitted when ordering. Be sure to refer to this chapter because this chapter also includes necessary information for systems development.
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-3 FEATURES ...................................................................................................................................... 1-3 PIN CONFIGURATION (TOP VIEW) ........................................................................................... 1-3 APPLICATION ................................................................................................................................ 1-3 BLOCK DIAGRAM ......................................................................................................................... 1-4 PERFORMANCE OVERVIEW ....................................................................................................... 1-5 DEFINITION OF CLOCK AND CYCLE ....................................................................................... 1-5 PIN DESCRIPTION ........................................................................................................................ 1-6 MULTIFUNCTION ................................................................................................................... 1-7 CONNECTIONS OF UNUSED PINS ................................................................................... 1-7 PORT FUNCTION .................................................................................................................. 1-7 PORT BLOCK DIAGRAMS .................................................................................................. 1-8 FUNCTIONAL BLOCK OPERATIONS ...................................................................................... 1-10 CPU ........................................................................................................................................ 1-10 PROGRAM MEMORY (ROM) ............................................................................................. 1-13 DATA MEMORY (RAM) ...................................................................................................... 1-14 INTERRUPT FUNCTION ..................................................................................................... 1-15 EXTERNAL INTERRUPTS .................................................................................................. 1-18 TIMERS ................................................................................................................................. 1-20 WATCHDOG TIMER ............................................................................................................ 1-24 CARRIER GENERATING CIRCUIT ................................................................................... 1-25 LCD FUNCTION ................................................................................................................... 1-28 RESET FUNCTION .............................................................................................................. 1-32 VOLTAGE DROP DETECTION CIRCUIT ......................................................................... 1-34 POWER DOWN FUNCTION ............................................................................................... 1-35 CLOCK CONTROL .............................................................................................................. 1-38 ROM ORDERING METHOD ....................................................................................................... 1-39 LIST OF PRECAUTIONS ............................................................................................................ 1-40 SYMBOL ........................................................................................................................................ 1-41 LIST OF INSTRUCTION FUNCTION ........................................................................................ 1-42 INSTRUCTION CODE TABLE .................................................................................................... 1-44 MACHINE INSTRUCTIONS ........................................................................................................ 1-46 CONTROL REGISTERS .............................................................................................................. 1-60 BUILT-IN PROM VERSION ........................................................................................................ 1-64 PIN CONFIGURATION (TOP VIEW) ......................................................................................... 1-64
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Table of contents CHAPTER 2 APPLICATION
2.1 I/O pins .................................................................................................................................... 2-2 2.1.1 I/O ports .......................................................................................................................... 2-2 2.1.2 Related registers ............................................................................................................ 2-4 2.1.3 Port application examples ............................................................................................. 2-6 2.1.4 Notes on use .................................................................................................................. 2-8 2.2 Interrupts ................................................................................................................................. 2-9 2.2.1 Interrupt functions .......................................................................................................... 2-9 2.2.2 Related registers .......................................................................................................... 2-10 2.2.3 Interrupt application examples .................................................................................... 2-12 2.2.4 Notes on use ................................................................................................................ 2-16 2.3 Timers .................................................................................................................................... 2-17 2.3.1 Timer functions ............................................................................................................. 2-17 2.3.2 Related registers .......................................................................................................... 2-17 2.3.3 Timer application examples ........................................................................................ 2-20 2.3.4 Notes on use ................................................................................................................ 2-24 2.4 Carrier generating circuit .................................................................................................. 2-25 2.4.1 Carrier functions ........................................................................................................... 2-25 2.4.2 Related registers .......................................................................................................... 2-26 2.4.3 Carrier wave output application examples ................................................................ 2-28 2.4.4 Notes on use ................................................................................................................ 2-32 2.5 LCD function ......................................................................................................................... 2-33 2.5.1 Operation description ................................................................................................... 2-33 2.5.2 Related registers .......................................................................................................... 2-34 2.5.3 LCD application examples .......................................................................................... 2-36 2.5.4 Notes on use ................................................................................................................ 2-38 2.6 Power down function .......................................................................................................... 2-39 2.6.1 Clock control function .................................................................................................. 2-41 2.6.2 Power down function ................................................................................................... 2-41 2.6.3 Related register ............................................................................................................ 2-44 2.6.4 Power down function application example ............................................................... 2-45 2.6.5 Notes on use ................................................................................................................ 2-45 2.7 Reset ....................................................................................................................................... 2-46 2.7.1 Reset circuit .................................................................................................................. 2-46 2.7.2 Internal state at reset .................................................................................................. 2-48 2.7.3 Voltage drop detection circuit ..................................................................................... 2-49 2.8 Oscillation circuit ................................................................................................................ 2-50 2.8.1 Oscillation circuit .......................................................................................................... 2-50 2.8.2 Oscillation operation .................................................................................................... 2-51 2.8.3 Notes on use ................................................................................................................ 2-51
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4551 Group User's Manual
Table of contents CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-4 3.1.4 Basic timing diagram ..................................................................................................... 3-5 3.2 Typical characteristics ......................................................................................................... 3-6 3.2.1 VDD-IDD characteristics ................................................................................................. 3-6 3.2.2 VOH-IOH characteristics (port CARR) .......................................................................... 3-9 3.2.3 VOL-IOL characteristics (Ports P0, P1, D0-D7, CARR, RESET) ............................ 3-10 3.2.4 Voltage drop detection circuit temperature characteristics .................................... 3-11 3.3 List of precautions .............................................................................................................. 3-12 3.4 Notes on noise ..................................................................................................................... 3-13 3.4.1 Shortest wiring length .................................................................................................. 3-13 3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................ 3-15 3.4.3 Oscillator concerns ....................................................................................................... 3-16 3.4.4 setup for I/O ports ....................................................................................................... 3-17 3.4.5 providing of watchdog timer function by software ................................................... 3-17 3.5 Mask ROM order confirmation form ............................................................................... 3-18 3.6 ROM programming order confirmation form ................................................................ 3-20 3.7 Mark specification form ..................................................................................................... 3-21 3.8 Package outline ................................................................................................................... 3-22
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List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 AMC instruction execution example ............................................................................... 1-10 2 RAR instruction execution example ............................................................................... 1-10 3 Registers A, B and register E ........................................................................................ 1-10 4 TABP p instruction execution example .......................................................................... 1-10 5 Stack registers (SKs) structure ....................................................................................... 1-11 6 Example of operation at subroutine call ....................................................................... 1-11 7 Program counter (PC) structure ..................................................................................... 1-12 8 Data pointer (DP) structure ............................................................................................. 1-12 9 SD instruction execution example .................................................................................. 1-12 10 ROM map of M34551E8 ................................................................................................ 1-13 11 Interrupt address page (addresses 008016 to 00FF16) structure ............................ 1-13 12 RAM map ......................................................................................................................... 1-14 13 Program example of interrupt processing ................................................................... 1-16 14 Internal state when interrupt occurs ............................................................................ 1-16 15 Interrupt system diagram ............................................................................................... 1-16 16 Interrupt sequence .......................................................................................................... 1-17 17 External interrupt circuit structure ................................................................................ 1-18 18 Auto-reload function ....................................................................................................... 1-20 19 Timers structure .............................................................................................................. 1-21 20 Watchdog timer function ................................................................................................ 1-24 21 Program example to enter the RAM back-up mode when using the watchdog timer .... 1-24 22 Carrier wave selection register ..................................................................................... 1-25 23 Carrier wave output auto-control by timer 1 .............................................................. 1-27 24 LCD clock control circuit structure ............................................................................... 1-28 25 LCD controller/driver structure ...................................................................................... 1-29 26 LCD RAM map ................................................................................................................ 1-30 27 LCD controller/driver structure ...................................................................................... 1-31 28 Reset release timing ...................................................................................................... 1-32 29 RESET pin input waveform and reset operation ....................................................... 1-32 30 Power-on reset circuit example .................................................................................... 1-32 31 Internal state at reset .................................................................................................... 1-33 32 Voltage drop detection reset circuit ............................................................................. 1-34 33 Voltage drop detection circuit operation waveform .................................................... 1-34 34 Set source and clear source of the P flag ................................................................. 1-36 35 Start condition identified example using the SNZP instruction .............................. 1-36 36 State transition ................................................................................................................ 1-37 37 Clock control circuit structure ....................................................................................... 1-38 38 Ceramic resonator external circuit ............................................................................... 1-39 39 Quartz-crystal oscillator external circuit ...................................................................... 1-39 40 External 0 interrupt program example ......................................................................... 1-40 41 Pin configuration of built-in PROM version ................................................................ 1-64 42 PROM memory map ....................................................................................................... 1-65 43 Flow of writing and test of the product shipped in blank ......................................... 1-65
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4551 Group User's Manual
List of figures CHAPTER 2 APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 2.1.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3.1 2.3.2 2.3.3 2.3.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.7.6 2.8.1 2.8.2 2.8.3 Key input by key scan ................................................................................................. 2-6 Input timing of key scan ............................................................................................. 2-7 External interrupt operation example ....................................................................... 2-12 External interrupt setting example ........................................................................... 2-13 Timer 1 constant period interrupt setting example ................................................ 2-14 Timer 2 constant period interrupt setting example ................................................ 2-15 Watchdog timer function............................................................................................ 2-20 Constant period measurement setting example ..................................................... 2-21 Constant period counter by timer 2 setting example ............................................ 2-22 Watchdog timer setting example .............................................................................. 2-23 Carrier wave selection register ................................................................................ 2-26 Carrier wave auto-control setting example 1 ......................................................... 2-28 Carrier wave auto-control setting example 2 ......................................................... 2-29 Carrier wave output interval setting example ......................................................... 2-30 Carrier wave by software generating example ...................................................... 2-31 LCD clock control circuit structure ........................................................................... 2-33 LCD RAM map ........................................................................................................... 2-34 LCD display panel example ...................................................................................... 2-36 Segment assignment example .................................................................................. 2-36 LCD RAM assignment example ............................................................................... 2-36 Initial setting example ................................................................................................ 2-37 State transition ............................................................................................................ 2-39 Oscillation stabilizing time in each mode ............................................................... 2-40 Start condition identified example ............................................................................ 2-43 Software setting example .......................................................................................... 2-45 Power-on reset circuit example ................................................................................ 2-46 Reset circuit example when the supply voltage rising time exceeds 100 ms .. 2-47 Oscillation stabilizing time after system is released from reset .......................... 2-47 Internal state at reset ................................................................................................ 2-48 Voltage drop detection reset circuit ......................................................................... 2-49 Voltage drop detection circuit operation waveform ............................................... 2-49 Oscillation circuit example connecting ceramic resonator externally .................. 2-50 Oscillation circuit example connecting quartz-crystal externally .......................... 2-50 Structure of clock control circuit .............................................................................. 2-51
CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 40 External 0 interrupt program example ......................................................................... 3-12 3.4.1 Selection of packages ............................................................................................... 3-13 3.4.2 Wiring for the RESET input pin ............................................................................... 3-13 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-14 3.4.4 Wiring for CNVSS pin ............................................................................................... 3-14 3.4.5 Wiring for the VPP pin of the One Time PROM version ...................................... 3-15 3.4.6 Bypass capacitor across the VSS line and the VCC line ...................................... 3-15 3.4.7 Wiring for a large current signal line ...................................................................... 3-16 3.4.8 Wiring to a signal line where potential levels change frequently ....................... 3-16 3.4.9 VSS pattern on the underside of an oscillator ....................................................... 3-16 3.4.10 Watchdog timer by software ................................................................................... 3-17
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List of tables
List of tabels
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Selection of system clock .................................................................................................. 1-5 1 ROM size and pages .................................................................................................... 1-13 2 RAM size ........................................................................................................................ 1-14 3 Interrupt sources ............................................................................................................ 1-15 4 Interrupt request flag, interrupt enable bit and skip instruction .............................. 1-15 5 Interrupt enable bit function ......................................................................................... 1-15 6 Interrupt control register ............................................................................................... 1-17 7 External interrupt activated condition ......................................................................... 1-18 8 External interrupt control register ................................................................................ 1-19 9 Function related timers ................................................................................................. 1-20 10 Timer control registers ................................................................................................ 1-22 11 Carrier generating circuit control register and control flag .................................... 1-26 12 Duty and maximum number of displayed pixels ..................................................... 1-28 13 LCD control registers .................................................................................................. 1-30 14 Port state at reset ....................................................................................................... 1-33 15 Functions and states retained at power down ........................................................ 1-35 16 Return source and return condition .......................................................................... 1-36 17 Pull-up control register ............................................................................................... 1-36 18 Clock control register .................................................................................................. 1-38 19 Product of built-in PROM version ............................................................................. 1-64 20 Programming adapter .................................................................................................. 1-65
CHAPTER 2 APPLICATION
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.1.1 2.1.2 2.1.3 2.1.4 2.2.1 2.2.2 2.3.1 2.3.3 2.3.2 2.3.4 2.4.1 2.4.2 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.8.1 Pull-up control register PU0 .................................................................................... 2-4 LCD control register L2 ............................................................................................ 2-4 Clock control register MR ........................................................................................ 2-5 connections of unused pins ..................................................................................... 2-8 Interrupt control register V1 ................................................................................... 2-10 Interrupt control register I1 .................................................................................... 2-11 Interrupt control register V1 ................................................................................... 2-17 Timer control register W2 ...................................................................................... 2-18 Timer control register W1 ...................................................................................... 2-18 Timer control register W3 ...................................................................................... 2-19 Carrier wave output control register C2 .............................................................. 2-27 Carrier wave generating control flag CR ............................................................. 2-27 Duty and maximum number of displayed pixels ................................................. 2-33 LCD control register L1 .......................................................................................... 2-34 LCD control register L2 .......................................................................................... 2-35 Timer control register W3 ...................................................................................... 2-35 Frame frequency ..................................................................................................... 2-38 Functions and states retained at RAM back-up mode and the clock operating mode .... 2-42 Return source and return condition ...................................................................... 2-43 Start condition identification ................................................................................... 2-43 Clock control register MR ...................................................................................... 2-44 Pull-up control register PU0 .................................................................................. 2-44 Maximum value of oscillation frequency and supply voltage ............................ 2-50
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4551 Group User's Manual
List of tables CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 Table 3.1.2 Recommended operating conditions ....................................................................... 3-3 Table 3.1.3 Electrical characteristics ........................................................................................... 3-4
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CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTIONAL BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS SYMBOL LIST OF INSTRUCTION FUNCTION INSTRUCTION CODE TABLE MACHINE INSTRUCTIONS CONTROL REGISTERS BUILT-IN PROM VERSION
HARDWARE
MEMO
1-2
4551 Group User's Manual
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 4551 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with an 8-bit timer with a reload register, a 14-bit timer which is also used as a watchdog timer, a 4-bit timer with a reload register, a carrier wave output circuit and an LCD control circuit. The mask ROM version and built-in PROM version of 4551 Group are produced as shown in the table below.
FEATURES
q Minimum instruction execution time ............................ 1.5 s (f(XIN)=8.0 MHz, VDD=5.0 V, system clock = f(XIN)/4) q Supply voltage ............................. 2.5 V to 5.5 V (One Time PROM version) ....................................... 2.2 V to 5.5 V (Mask ROM version) q System clock switch function ........................................... Clock divided by 4 or not divided
q LCD control circuit Segment output .................................................................. 20 Common output ....................................................................4 q Carrier wave frequency switch function System clock, system clock/2, system clock/8, system clock/12, system clock/16, system clock/24, "H" fixed q Timers Timer 1 ................................ 8-bit timer with a reload register Timer 2 ............... 14-bit timer also used as a watchdog timer Timer LC ............................. 4-bit timer with a reload register q Interrupt ................................................................... 3 sources q Voltage drop detection circuit ............................................... 1 q Clock generating circuit (ceramic resonance and quartz-crystal oscillation)
APPLICATION
Remote control transmitter
Product M34551M4-XXXFP M34551M8-XXXFP (Note 1)
ROM (PROM) size (! 10 bits) 4096 words 8192 words 8192 words
RAM size (! 4 bits) 280 words 280 words
Package 48P6S-A 48P6S-A 48P6S-A
ROM type Mask ROM Mask ROM One Time PROM
280 words M34551E8-XXXFP (Note 2) Notes 1: Under development (Aug. 1998) 2: Shipped after writing (shipped in blank: M34551E8FP)
M34551Mx-XXXFP
36
35
34
37
38
33
32
31
SEG9 SEG10 SEG11 SEG12 VSS SEG13 SEG14 SEG15 P20 / SEG16 P21 / SEG17
39 40 41 42 43 44 45 46 47 48
10 11 12 13 14 2 1 3 4 5 6 7 8 9
30
29
28
27
26
25
RESET
24 23 22 21
PIN CONFIGURATION (TOP VIEW)
COM2 COM3 COM1 COM0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG8 SEG2 SEG1 SEG0
D7/XCOUT D6/XCIN CNVSS XOUT XIN VSS VDD CARR D5 / INT D4
M34551Mx-XXXFP
20 19 18 17 16 15
P00
P03
P10
P11
P01
P23 / SEG19
P02
P22 / SEG18
P12
P13
D0
D1
D2
Outline 48P6S-A
4551 Group User's Manual
D3
1-3
1-4
4 8 4
4
BLOCK DIAGRAM
HARDWARE
BLOCK DIAGRAM
I/O port
Port P1 Port P2 Port D
Port P0
Internal peripheral functions
System clock generating circuit
Timers
Timer 1 (8 bits) Timer 2 (14 bits) Remote control carrier wave output
Timer LC (4 bits)
XIN -XOUT (Main clock) XCIN -XCOUT (Sub-clock)
Memory 4500 Series CPU core
ALU(4 bits)
Register B (4 bits) Register A (4 bits) Register E (8 bits) Register D (3 bits) Stack registers SKs (8 levels) Interrupt stack register SDP(1 level)
ROM (Note)
4096 to 8192 words ! 10 bits
4551 Group User's Manual
RAM
280 words ! 4 bits (LCD RAM 20 words ! 4 bits included)
LCD drive control circuit (max. 20 segments ! 4 common)
Segment output 4
Common output
20
Note: PROM 8192 words ! 10 bits
HARDWARE
PERFORMANCE OVERVIEW
PERFORMANCE OVERVIEW
Parameter Number of basic instructions 92 Function Minimum instruction execution time 1.5 s (f(XIN) = 8.0 MHz:system clock = f(XIN)/4: VDD = 5.0 V) Memory sizes ROM M34551M4 4096 words ! 10 bits M34551M8 8192 words ! 10 bits M34551E8 8192 words ! 10 bits 280 words ! 4 bits (LCD RAM 20 words ! 4 bits included) Eight independent output ports 4-bit I/O port; each pin is equipped with a pull-up function. 4-bit I/O port; each pin is equipped with a pull-up function. 4-bit input port 1-bit output port (CMOS output) 8-bit timer with a reload register 14-bit timer/ Fixed dividing frequency timer 4-bit timer with a reload register 3 (one for external and two for timer) 1 level 8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction is executed) LCD Selective bias value 1/2, 1/3 bias Selective duty value 2, 3, 4 duty 4 Common output 20 Segment output Internal resistor for 200 k ! 3 power supply Device structure Package Operating temperature range Supply voltage Power at active dissipation at clock operating (typical value) at RAM back-up CMOS silicon gate 48-pin plastic molded QFP -20 C to 70 C 2.2 V to 5.5 V (One Time PROM version: 2.5 V to 5.5 V) 2.5 mA (f(XIN) = 8.0 MHz system clock = f(XIN)/4, VDD=5 V) 27.5 A (at main clock oscillation stop, sub-clock oscillation frequency: 32.0 kHz, Ta=25C, VDD=5 V) 0.1 A (at main clock oscillation stop, sub-clock oscillation stop, Ta=25 C, VDD=5V) q Instruction clock (INSTK) The instruction clock is the standard clock for controlling CPU. The instruction clock is a signal derived from dividing the system clock by 3. The one cycle of the instruction clock is equivalent to the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction.
RAM Input/Output ports D0-D7
Output P00-P03 I/O P10-P13 I/O P20-P23 Input Output CARR Timer 1 Timer 2/ Watchdog timer Timer LC
Timers
Interrupt
Sources
Nesting Subroutine nesting
DEFINITION OF CLOCK AND CYCLE
q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock can be selected by bits 0 and 3 of the clock control register MR as shown in the table below. Table Selection of system clock Register MR System clock (STCK) MR3 MR0 f(XIN) 0 0 f(XIN)/4 0 f(XCIN)/4 1 1 Note: f(XIN)/4 is selected immediately after system is released from reset. 0 1 1 f(XCIN)
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HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Pin VDD VSS CNVSS
RESET
Name Power supply Ground CNVSS Reset input
Input/Output Function -- Connected to a plus power supply. -- Connected to a 0 V power supply. Input I/O Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. A pull-up resistor is built-in this pin. When the watchdog timer causes the system to be reset or the lowsupply voltage is detected, the RESET pin outputs "L" level.
XIN XOUT D0-D4 D5/INT
Main clock input Main clock output Output port D Output port D/ Interrupt input
Input Output Output I/O
I/O pins of the main clock generating circuit. A ceramic resonator can be connected between XIN pin and XOUT pin. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. 1-bit output port. Port D5 is also used as an INT input pin. When D5/INT pin is used as the INT input pin, set the output latch to "1." The output structure is Nchannel open-drain. Each pin of port D has an independent 1-bit output function. Ports D6 and D7 are also used as pins XCIN and XCOUT for the sub-clock generating circuit, respectively. When pins D6/XCIN and D7/XCOUT are used as the pins for the sub-clock generating circuit, a 32.0 kHz quartz-crystal oscillator can be connected between XCIN pin and XCOUT pin. A feedback resistor is built-in between them. 4-bit I/O port. It can be used as an input port when the output latch is set to "1." The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function.
D6/XCIN
Output port D/ Sub-clock input
I/O
D7/XCOUT
Output port D/ Sub-clock output
Output
P00-P03
I/O port P0
I/O
P10-P13
I/O port P1
I/O
4-bit I/O port. It can be used as an input port when the output latch is set to "1." The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. 4-bit input port. Ports P20-P23 are also used as the segment output pins SEG16- SEG19, respectively. Carrier wave output pin for remote control transmit. The output structure is the CMOS circuit. LCD segment output pins. LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0- COM2 are used at 1/3 duty and pins COM0-COM3 are used at 1/4 duty.
P20/SEG16- Input port P2/ P23/SEG19 Segment output CARR Carrier wave output for remote control SEG0-SEG15 Segment output COM0-COM3 Common output
I/O Output Output Output
1-6
4551 Group User's Manual
HARDWARE
PIN DESCRIPTION
MULTIFUNCTION
Pin D5 D6 D7 P20 P21 INT XCIN XCOUT SEG16 SEG17 Multifunction INT XCIN XCOUT SEG16 Pin D5 D6 D7 P20 P21 P22 P23 Multifunction
SEG17 P22 SEG18 SEG18 P23 SEG19 SEG19 Notes 1: Pins except above have just single function. 2: The ports D5-D7 are the output port and ports P20-P23 are the input ports.
CONNECTIONS OF UNUSED PINS
Pin D0-D4 D5/INT D6/XCIN Connection Pin Connect to VSS, or set the output latch to CARR "0" and open. SEG0-SEG15 Select ports D6 and D7 and connect to VSS, COM0-COM3 or set the output latch to "0" and open. P00-P03 Connection Open Open Open Set the output latch to "1" and open. Open or connect to VSS (Note)
D7/XCOUT P 2 0 / S E G 1 6 - P 2 3 / Select port P2 and connect to VSS, or select P10-P13 SEG19 the segment output function and open.
Note: In order to connect ports P10-P13 to VSS, turn off their pull-up transistors (Pull-up control register PU0i="0") by software. In order to make these pins open, turn on their pull-up transistors (register PU0i="1") by software, or turn off their pull-up transistors (register PU0i="0") and set the output latch to "0" (i = 0, 1, 2, or 3). Be sure to select the key-on wakeup function and the pull-up function with every one port. (Note in order to set the output latch to "0" and make pins open) * After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to "0" by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. * To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note in order to connect unused pins to VSS or VDD) * To avoid noise, connect the unused pins to VSS or VDD at the shortest distance using a thick wire.
PORT FUNCTION
Port Port D Pin D0-D4, D5/INT, D6/XCIN, D7/XCOUT Port P0 Port P1 P00-P03 P10-P13 I/O (4) I/O (4) N-channel open-drain N-channel open-drain 4 4 Input/ Output Output (8) Output structure N-channel open-drain Control bits 1 Control Control instructions registers SD MR RD CLD OP0A IAP0 OP1A IAP1 PU0 Pull-up functions Key-on wakeup functions Pull-up functions (programmable) Key-on wakeup functions (programmable) Port P2 P20/SEG16- P23/SEG19 Input (4) 4 IAP2 Remark
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HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS
Key-on wakeup input Register A Ai Ai OP0A instruction PU0i Key-on wakeup input Register A Ai Ai OP1A instruction DQ T LCD power supply LCD control signal (Note 1) Connected to when selecting SEG IAP1 instruction DQ T Pull-up transistor (Note 1) IAP0 instruction Pull-up transistor (Note 1)
P00-P03
P10-P13
P20/SEG16-P23/SEG19
L2i Register A
IAP2 instruction
LCD power supply
Register Y
Decoder (Note 1) CLD instruction S
SD instruction RD instruction
D0-D4
RQ (Note 1)
Register Y
Decoder CLD instruction
INT input
D5/INT
S SD instruction RD instruction Register Y Decoder CLD instruction S SD instruction RD instruction RQ
1
RQ (Note 1) MR2
0
D6/XCIN
MR2 MR2 XCIN clock (Note 1) MR2 S RQ
0 1
Register Y
Decoder CLD instruction
D7/XCOUT
SD instruction RD instruction
Notes 1: This symbol represents a parasitic diode. 2: i represents bit 0, 1, 2 or 3.
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PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
To timer 1 TC1A instruction
CARRY
Register C1
Carrier wave output circuit (Note)
CR flag
STCR instruction SPCR instruction SQ R
W31
CARR
Timer LC underflow signal
F/F
W30
Timer 1 underflow signal
F/F
C20
W20
LCD power supply LCD control signal Pch SEG0-SEG15 Nch
LCD control signal LCD power supply
LCD power supply LCD control signal Pch COM0-COM3 Pch
LCD control signal LCD power supply
LCD power supply LCD control signal
Nch
LCD control signal
Nch
Note: This symbol represents a parasitic diode.
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
FUNCTIONAL BLOCK OPERATIONS CPU

(1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag (CY) Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
(CY) (M(DP)) Addition (A)
Fig. 1 AMC instruction execution example
ALU
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A
TBA instruction
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address
ROM 8 4 0
PCH p6 p5 p4 p3 p2 p1 p0
PCL DR2DR1DR0 A3 A2 A1 A0
Low-order 4 bits Register A (4) Middle-order 4 bits Register B (4)
Immediate field value p
The contents of The contents of register D register A
Fig. 4 TABP p instruction execution example
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FUNCTIONAL BLOCK OPERATIONS
(5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used when using an interrupt service routine or when executing a table reference instruction. Accordingly, be careful not to stack over when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Multiple interrupts cannot be used. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.
Program counter (PC) Executing the subroutine Executing the return or call or table reference table reference instruction instruction SK0 (SP) = 0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7
Stack pointer (SP) points "7" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) (SK0) (PC)
0 000116 SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(PC) (SP)
(SK0) 7
Note: Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD or RD instruction (Figure 9).
Program counter (PC) p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
Register Y (4) Register X (4)
Specifying RAM digit
Specifying RAM file
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D7 D6 D5 D4 D0
0
1
0
1
1 Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
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FUNCTIONAL BLOCK OPERATIONS
PROGRAM MEMORY (ROM)
1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34551E8. Table 1 ROM size and pages Product M34551M4 M34551M8 M34551E8 ROM size (! 10 bits) 4096 words 8192 words 8192 words Pages 32 (0 to 31) 64 (0 to 63) 64 (0 to 63)
98 000016 007F16 008016 00FF16 010016 017F16 018016
7
6
5
4
32
10 Page 0
Interrupt address page Subroutine special page
Page 1 Page 2 Page 3
0FFF16
Page 31
A top part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
1FFF16
Fig. 10 ROM map of M34551E8
Page 63
008016
98 7 6 5 4 3 2 10 External 0 interrupt address
008416 008616
Timer 1 interrupt address Timer 2 interrupt address
00FF16
Fig. 11 Interrupt address page (addresses 008016 to 00FF16) structure
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Also, be sure to set a value to the data pointer certainly when returning from power down. RAM includes the area corresponding to the LCD. A segment is turned on automatically when "1" is written in the bit corresponding to the segment. Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size Product M34551M4 M34551M8 M34551E8
RAM size 280 words ! 4 bits (1120 bits)
RAM 280 words ! 4 bits (1120 bits) Register Z 0 Register X 0 1 2 3 *** 6 7 ****** 15 0 1 2 3 4 5
0
1 1
2
Register Y
6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19
280 words Notes 1: The area marked "-" (Z = 1, X = 0 to 2, Y = 0 to 7) is not a memory area. 2: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig. 12 RAM map
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FUNCTIONAL BLOCK OPERATIONS
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * Interrupt enable flag (INTE) = "1" (Interrupt enabled) * Interrupt enable bit = "1" (Interrupt request occurrence enabled) * An interrupt activated condition is satisfied (request flag = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bits (V10-V13) Use an interrupt enable bit of interrupt control register V1 to select the corresponding interrupt request or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.
Table 3 Interrupt sources Interrupt Priority Activated condition Interrupt name address level Address 0 1 External 0 interrupt Level change of in page 1 INT pin 2 Timer 1 underflow Address 4 Timer 1 interrupt in page 1 3 Timer 2 interrupt Timer 2 underflow Address 6 in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip instruction Request flag Enable bit Skip instruction Interrupt name EXF0 V10 SNZ0 External 0 interrupt Timer 1 interrupt Timer 2 interrupt T1F T2F V12 V13 SNZT1 SNZT2
Table 5 Interrupt enable bit function Occurrence of Interrupt enable bit interrupt request 1 0 Enabled Disabled
Skip instruction Invalid Valid
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after a branch to a sequence for storing data into stack register is performed. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return to main routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning to the main routine. (Refer to Figure 13)
*Program counter (PC) ........................................................ Each interrupt address *Stack register (SK) .......... The address of main routine to be executed when returning *Interrupt enable flag (INTE) ........................................................... 0 (Interrupt disabled) *Interrupt request flag (only the flag for the current interrupt source) ........................................................................................... 0 *Data pointer, carry flag, registers A and B, skip flag ...... Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs
INT pin (L H or H L input)
EXF0
V10
Address 0 in page 1 Address 4 in page 1
Timer 1 underflow Timer 2 underflow Activated condition
T1F
V12
Main routine
Interrupt service routine Interrupt occurs
T2F Request flag (state retained)
V13 Enable bit
INTE Enable flag
Address 6 in page 1
Fig. 15 Interrupt system diagram
Interrupt is enabled
EI RTI
: Interrupt enabled state : Interrupt disabled state
Fig. 13 Program example of interrupt processing
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FUNCTIONAL BLOCK OPERATIONS
(6) Interrupt control register q Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register Table 6 Interrupt control register Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1
through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
at reset : 00002
at power down : 00002
R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid)
Note: "R" represents read enabled, and "W" represents write enabled. (7) Interrupt sequence Interrupts occur only when the respective INTE flag, interrupt enable bits (V10-V13), and interrupt request flags (EXF0, T1F, T2F) are "1." The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).
q When an interrupt request flag is set after its interrupt is enabled
1 machine cycle
System clock (STCK)
Interrupt enable flag (INTE)
"1" "0"
EI instruction execution cycle Interrupt enabled state
Interrupt disabled state
INT pin External interrupt EXF0 flag
"H" "L" "1" "0" Interrupt activated condition is satisfied.
Retaining level for 4 cycles or more of STCK is necessary.
Timer 1 and Timer 2 interrupts
"1" T1F, T2F "0" flags Flag cleared 2 to 3 machine cycles (Note 1, 2) Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. Software starts from the interrupt address.
Fig. 16 Interrupt sequence
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
EXTERNAL INTERRUPTS
An external interrupt request occurs when a valid waveform (= waveform causing the external 0 interrupt) is input to an interrupt input pin (edge detection). The external 0 interrupt can be controlled with the interrupt control register I1. Table 7 External interrupt activated condition Name External 0 interrupt Input pin D5/INT Valid waveform Falling waveform ("H""L") Rising waveform ("L""H") Valid waveform selection bit (I12) 0 1
I12
Falling
0 D5/INT 1
Rising One-sided edge detection circuit
EXF0 Skip
External 0 interrupt
SNZI0 instruction
Fig. 17 External interrupt circuit structure
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FUNCTIONAL BLOCK OPERATIONS
(1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to D5/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. The D5/INT pin need not be selected the external interrupt input INT function or the normal output port D5 function. However, the EXF0 flag is set to "1" when a valid waveform output from port D5 is input to INT pin even if it is used as an output port D5. q External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D5/INT pin. The valid waveform can be selected from rising waveform or falling waveform. An example of how to use the external 0 interrupt is as follows. Select the valid waveform with the bit 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the D5/INT pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs. Table 8 External interrupt control register Interrupt control register I1 I13 Not used 0 1 0 I12 Interrupt valid waveform for INT pin selection bit (Note 2) 1 0 1 0
(2) External interrupt control register q Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.
at reset : 00002
at power down : state retained
R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction) Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)
I11 I10
Not used Not used
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled. 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to "1" when the contents of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction.
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
TIMERS
The 4551 Group has the following timers. q Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a set value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
q Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" every n count of a count pulse.
FF16 n : Counter initial value Count starts n
The contents of counter
Reload
Reload
1st underflow
2nd underflow
0016 Time n+1 count Timer 1 interrupt "1" request flag "0" An interrupt occurs or a skip instruction is executed. n+1 count
Fig. 18 Auto-reload function The 4551 Group timer consists of the following circuits. * Prescaler : frequency divider * Timer 1 : 8-bit programmable timer * Timer 2 : 14-bit fixed dividing frequency timer * Timer LC : 4-bit programmable timer (Timers 1 and 2 have the interrupt function, respectively) Table 9 Function related timers Circuit Prescaler Timer 1 Structure Frequency divider 8-bit programmable binary down counter Timer 2 Count source * Instruction clock (INSTCK) * Prescaler output (ORCLK) * Carrier generating circuit output (CARRY, CARRY/2) 16384 * f(XCIN) 1 to 16 Frequency dividing ratio 4, 8 1 to 256 Use of output signal * Timer 1 and 2 count sources * Timer 1 interrupt * Port CARR output control * Timer 2 interrupt * Divider for LCD * Watchdog timer * Divider for LCD * Carrier output W3 Control register W1 W1 W2 W2 Prescaler, timer 1, timer 2 and timer LC can be controlled with the timer control registers W1, W2 and W3. Each function is described below.
14-bit fixed dividing * Prescaler output (ORCLK) frequency
Timer LC
4-bit programmable * Bit 3 of timer 2 binary down counter * System clock (STCK)
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FUNCTIONAL BLOCK OPERATIONS
INSTCK Frequency dividing circuit (divided by 4) MR3
1 0
Prescaler W13
0
W12 1/4 1/8
0
MR0
XIN XCIN
0 1
Frequency dividing circuit (divided by 3) STCK
ORCLK
1 1
W11, W10
ORCLK CARRY
00,01 10
W20 (Note 1)
0 1
Timer 1 (8)
T1F
Timer 1 interrupt
1
11
2
(TAB1)
Reload register R1 (8) (T1AB) (Note 2) Register B Register A
Carrier wave output control
W30 (Note 1) W31 STCK
1 0 WRST instruction 0 1
To port CARR Timer LC (4) Reload register RLC (4)
Count source
1
2
LCD clock
S
WEF
W23 (Note 3)
0
Q
Reset signal
R
ORCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13
1 Count source
Timer 2
WDF
D T
Q
System reset
W22, W21
00 01 Not available 10,11
T2F
Timer 2 interrupt
Notes 1: Count source is stopped by setting to "0." 2: When the T1AB instruction is executed after setting W20 to "1," data is written only to reload register R1. 3: When the contents of W2 3 changes from "0" to "1," the count value of timer 2 is initialized.
Fig. 19 Timers structure
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FUNCTIONAL BLOCK OPERATIONS
Table 10 Timer control registers Timer control register W1 W13 W12 Prescaler control bit Prescaler dividing ratio selection bit 0 1 0 1
W11 W10
at reset : 00002
at power down : 00002
R/W
Stop (prescaler state initialized) Operating Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 8 Count source Prescaler output (ORCLK)
W11 Timer 1 count source selection bits W10
0 0 1 1
0 1
0 Carrier output (CARRY) 1 Carrier output divided by 2 (CARRY/2)
Timer control register W2 W23 Timer 2 count source selection bit 0 1
at reset : 10002
at power down : - - - 02
R/W
f(XCIN) Prescaler output (ORCLK) Count source Underflow occur every 2 count Underflow occur every 213 count Not available Not available Stop (timer 1 state retained) Operating
14
W22 W21
W22 Timer 2 count value selection bits W21
0 0 1 1 0 1
0 1 0 1
W20
Timer 1 control bit
Timer control register W3 W31 W30 Timer LC count source selection bit Timer LC control bit 0 1 0
at reset : 002
at power down : state retained
R/W
Bit 3 of timer 2 is output (timer 2 count source divided by 16) System clock (STCK) Stop (timer LC state retained)
1 Operating Note: "R" represents read enabled, and "W" represents write enabled. "-" represents state retained. (1) Timer control registers q Timer control register W1 Register W1 controls the count source of timer 1, the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. q Timer control register W2 Register W2 controls the count operation of timer 1 and count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. q Timer control register W3 Register W3 controls the count operation and count source of timer LC. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.
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FUNCTIONAL BLOCK OPERATIONS
(2) Precautions Note the following for the use of timers. q Prescaler Stop the prescaler operation to change its frequency dividing ratio. q Count source Stop timer 1 or timer LC counting to change its count source. When timer 2 count source changes from f(XCIN) to ORCLK (W23 = "0" W23 = "1"), the count value of timer 2 is initialized. However, when timer 2 count source changes from ORCLK to f(XCIN) (W23 = "1" W23 = "0") or the same count source is set again (W23 = "0" W23 = "0" or W23 = "1" W23 = "1"), the count value of timer 2 is not initialized. q Timer 2 Timer 2 has the watchdog timer function (WDT). When timer 2 is used as the WDT, note that the processing to initialize the count value and the execution of the WRST instruction. q Reading the count value Stop the prescaler and then execute the TAB1 instruction to read timer 1 data. q Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. (3) Prescaler Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock (INSTCK). Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. When the bit 3 of register W1 is cleared to "0," prescaler is initialized, and the output signal (ORCLK) stops. (4) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). When timer 1 stops, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer 1 is operating, data can be set only in the reload register (R1) with the T1AB instruction. When setting the next count data to reload register R1 while timer 1 is operating, be sure to set data before timer 1 underflows. Timer 1 starts counting after the following process; set data in timer 1, select the count source with bits 0 and 1 of register W1, set the bit 0 of register W2 to "1." Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (autoreload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 to registers A and B. Stop counting and then execute the TAB1 instruction to read its data.
(5) Timer 2 (interrupt function) Timer 2 is a 14-bit binary down counter. Timer 2 starts counting after the following process; select the count source with the bit 3 of register W2, and the clock as a count source is supplied. Timer 2 stops counting and its count value is retained when supply of a clock as a count source stops. Timer 2 is initialized at reset and when the count source changes from f(XCIN) (W23="0") to ORCLK (W23="1"). The count value to set the timer 2 interrupt request flag (T2F) to "1" can be selected from every 8192 count or every 16384 count with bits 1 and 2 of register W2. The count source signal divided by 16 is output from timer 2. Timer 2 can be used as a counter for clock in the clock operating mode (POF instruction executed). (6) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Timer LC starts counting after the following process; set data in timer LC, select the count source with the bit 1 of register W3, set the bit 0 of register W3 to "1." Timer LC is the timer for LCD clock generating. Also, it can be used as the multi-carrier generator by setting the bit 1 of register W3 to "1" and selecting the system clock (STCK) as a count source. When the multi-carrier generator is selected, the waveform which is the timer LC underflow signal divided by 2 can be output as a carrier wave from port CARR. At this time, stop the carrier generating circuit and LCD control circuit. When the multi-carrier generator (duty ratio: 1/2 fixed) is used, the enable/stop of the carrier wave output from port CARR can be set by the stop of timer LC or the carrier wave output auto-control function by timer 1. (7) Timer interrupt request flags (T1F and T2F) Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1 and SNZT2). Use the interrupt control register V1 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction.
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of timer 2, watchdog timer enable flag (WEF), and watchdog timer flag (WDF). When the WRST instruction is executed after system is released from reset, the WEF flag is set to "1." At this time, the watchdog timer starts operating. When the WEF flag is set to "1," it cannot be cleared to "0" until system reset is performed. Also, when the WRST instruction is not executed once, watchdog timer does not operate because the WEF flag retains "0." When the watchdog timer is operating, the WDF flag is set to "1" every time the bit 12 of timer 2 is cleared from "1" to "0." This means that count is performed 8192 times. When the bit 12 of
timer 2 is cleared from "1" to "0" while the WDF flag is set to "1," the internal reset signal is generated and system reset is performed. The WDF flag can be cleared to "0" with the WRST instruction. In the RAM back-up mode, though timer 2 count operation stops, its count value is retained and the WDF flag is initialized. In the clock operating mode, timer 2 count operation is continued and the WDF flag is initialized. When using the watchdog timer, execute the WRST instruction at a certain cycle which consists of timer 2's 8191 counts or less to keep the microcomputer operation normal.
3FFF16
Value of timer 2
0000 16
WEF flag "1" "0" "1" "0" "H" "L" System reset
WRST instruction WRST instruction execution execution
WDF flag
Internal reset signal
Fig. 20 Watchdog timer function The contents of the WDF flag are initialized in the RAM back-up mode. If the WDF flag is set to "1" at the same time that the microcomputer enters the RAM back-up mode, system reset may be performed. When using the watchdog timer and the RAM back-up mode, initialize the WDF flag with the WRST instruction just before the microcomputer enters the RAM back-up mode (refer to Figure 21).
* * * * * * WRST EPOF POF2
; Clear WDF flag ; POF instruction execution enabled
Oscillation stop (RAM back-up mode)
Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
CARRIER GENERATING CIRCUIT
The 4551 Group has a carrier generating circuit that generates the transfer waveform by dividing the system clock (STCK) for each remote control carrier wave. Each carrier waveform can be output by setting the carrier wave selection register (C1). Also, timer 1 can auto-control the carrier wave output from port CARR by setting the carrier wave output control register (C2).
Carrier wave selection register C1
Register C1 Setting value
C13 C12 C11 C10
STCR instruction
(at reset: 0 1 1 1 2, at power down: 0 1 1 1 2, W) Output waveform
SPCR instruction
Carrier wave Frequency Duty
0
0
0
0
"H" "L"
1/3
STCK/24
0
0
0
1
"H" "L"
1/2 1/4
STCK/16
0
0
1
0
"H" "L"
0
0
1
1
"H" "L"
1/2
STCK/2
0 0 1 0 1 0 1 1
1 1 1 1 1 1 1 0
0 0 0 1 1 1 1 0
0 1 1 0 0 1 1 0
"H" "L"
1/2
"H" "L"
No carrier wave
No available
"H" "L"
"L" fixed
"H" "L"
1/3
STCK/12
1
0
0
1
"H" "L"
1/2 1/4
STCK/8
1
0
1
0
"H" "L"
1
0
1
1
"H" "L"
1/2
STCK
1
1
0
0
"H" "L"
1/2
Note:"W" represents write enabled.
Fig. 22 Carrier wave selection register
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FUNCTIONAL BLOCK OPERATIONS
Table 11 Carrier generating circuit control register and control flag Carrier wave output control register C2 C20 Carrier wave output auto-control bit 0 1 at reset : 02 at power down : 02 W
Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid
Carrier wave generating control flag CR CR Carrier wave generating control 0 1
at reset : 02
at power down : 02
W
Carrier wave generating stop (SPCR instruction) Carrier wave generating start (STCR instruction)
Note: "W" represents write enabled. (1) Carrier generating circuit related registers q Carrier wave selection register C1 Each carrier waveform can be selected by setting the register C1. Set the contents of this register through register A with the TC1A instruction. q Carrier wave output control register C2 Timer 1 can auto-control the output enable interval and the output disable interval of the carrier wave output from port CARR by setting the register C2. Set the contents of this register through register A with the TC2A instruction. The setting of the output enable/disable interval is described below. Validate the carrier wave output auto-control function (C20="1"). Select the carrier wave or the carrier wave divided by 2 as the timer 1 count source. Set the count value (the output enable interval of carrier wave from port CARR) to timer 1. Operate timer 1 (W20="1"). Operate the carrier generating circuit (STCR instruction executed). Set the next count value (the output disable interval of carrier wave from port CARR) to reload register R1 before timer 1 underflow occurs. The carrier wave is output from port CARR until the first timer 1 underflow occurs. The output of the carrier wave from port CARR is disabled and the next count value is loaded from reload register R1 to timer 1 by the first timer 1 underflow. Then, the output of carrier wave is disabled until the second timer 1 underflow. Also, the next enable interval of the carrier wave output can be set by setting the third count value to timer 1 reload register before the second timer 1 underflow occurs. If the carrier wave output auto-control function is invalidated (C20="0") while the carrier wave output is autocontrolled, the output of port CARR retains the state when the auto-control is invalidated regardless of timer 1 underflow. This state can be terminated by timer 1 stop (W20="0"). When the carrier wave output auto-control function is validated (C20="1") again after it is invalidated (C20="0"), the autocontrol of carrier wave output is started again when the next timer 1 underflow occurs. (2) Carrier wave generating control flag (CR) The CR flag is used to control the carrier wave generating operation of the carrier generating circuit. The CR flag is "1" and the carrier wave generating is started by executing the STCR instruction. The CR flag is "0" and the carrier wave generating is stopped by executing the SPCR instruction. The CR flag is "0" at system reset. (3) Note on the carrier generating circuit stop In order to stop the carrier wave which has the cycle longer than that of the instruction clock with the SPCR instruction, stop it at the point when the carrier wave outputs "L" level in the SPCR instruction execution cycle. If this condition is not satisfied, the last "H" output interval of carrier wave is shortened. (4) Notes when using the carrier wave output auto-control function q Execute the STCR instruction after setting the timer 1 and register C2 in order to start the carrier generating circuit operation. q Stop the timer 1 (W20="0") after stopping the carrier generating circuit (SPCR instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. q If the carrier wave output auto-control function is invalidated (C20="0") while the carrier wave output is auto-controlled, the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This state can be terminated by timer 1 stop (W20="0"). When the carrier wave output auto-control function is validated (C20="1") again after it is invalidated (C20="0"), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur. q Use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output autocontrol function is selected. If the ORCLK is used as the count source, a hazard may occur in port CARR output because ORCLK is not synchronized with the carrier wave. q When "no carrier wave" is selected with register C1 ((C13C12C11C10) = (0101), (1101)), the enable/disable of the carrier wave output cannot be controlled by the carrier wave output auto-control function.
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FUNCTIONAL BLOCK OPERATIONS
Timer 1 start
Timer 1 underflow Port CARR output (C20)1
"1" "0"
"H" "L"
a
b
c
d
Set the interval Set the interval "b" to "a" to timer 1. reload register R1.
Set the interval "c" to reload register R1.
Set the interval "d" to reload register R1.
Carrier wave output start
Timer 1 underflow
"1" "0"
Port CARR output
"H" "L"
Register C20
"1" "0"
Carrier wave output start
(C20)0
(C20)1 (C20)0
(C20)1
Fig. 23 Carrier wave output auto-control by timer 1
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
LCD FUNCTION
The 4551 Group has an LCD (Liquid Crystal Display) controller/ driver. When data are set in timer control registers (W2, W3), timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. When the required number of segment pins is 19 or less, pins SEG16-SEG19 (4) can be used as input ports P20-P23. (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. q 1/2 duty, 1/2 bias q 1/3 duty, 1/3 bias q 1/4 duty, 1/3 bias Table 12 Duty and maximum number of displayed pixels (2) LCD clock control Duty Maximum number of displayed pixels Used COM pins 1/2 1/3 40 segments 60 segments COM0, COM1 (Note) COM0-COM2 (Note) COM0-COM3
The LCD clock is determined by the timer 2 count source selection bit (W23), timer LC control bit (W30), and timer LC. Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Numbers ( to ) shown below the formula correspond to numbers in Figure 24, respectively. q When using the prescaler output (ORCLK) as timer 2 count source (W23="1") F = ORCLK ! 1 16 ! ! 1 LC + 1 1 2
q When using the f(XCIN) as timer 2 count source (W23="0") F = f(XCIN) ! 1 16 ! 1 LC + 1 ! 1 2

[LC: 0 to 15]
The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = n F F n (s) F: LCD clock frequency 1/n: Duty (Hz)
Frame period =
1/4 80 segments Note: Leave unused COM pins open.

(Note)
W23 XCIN ORCLK
0 1
W31
1 0
W30
0 1
STCK 1/16
Timer LC
1/2
LCD clock
Note: Count source is stopped by clearing to "0."
Fig. 24 LCD clock control circuit structure
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COM0 COM2 COM1 COM3 SEG0 SEG15 ................. P20/SEG16
(Note) VLC3
- - P23/SEG19
Multiplexer
................. Control signal
Fig. 25 LCD controller/driver structure
Multiplexer
Common driver Bias control
Segment ... driver Segment driver Segment driver
Selector Selector Selector
...
...
Decoder RAM RAM
RAM
4551 Group User's Manual
1/2, 1/3, 1/4 Counter
LCD clock (from timer block)
LCD on/off control
L13 L12 L11 L10
L23 L22 L21 L20
Register A
Note: VLC3=VDD.
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When "1" is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed.
(4) LCD drive waveform When "1" is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lVLC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes VLC3 level (=VDD).
Z X Y 8 9 10 11 12 13 14 15 COM
Bit
0 3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM3 2 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM2 1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM1 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 3 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM3
1 1 2 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM2 1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM1 0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 3 SEG16 SEG17 SEG18 SEG19
2 2 1 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19
0 SEG16 SEG17 SEG18 SEG19
COM3 COM2 COM1 COM0
Note: The area marked "
" is not the LCD display RAM.
Fig. 26 LCD RAM map Table 13 LCD control registers LCD control register L1 L13 L12 Not used LCD on/off bit 0 1 0 1
L11 L10
at reset : 00002
at power down : state retained
R/W
This bit has no function, but read/write is enabled Off On Duty Not available 1/2 1/3 1/4 1/2 1/3 1/3 Bias 0 1 0 1
L11 LCD duty and bias selection bits L10
0 0 1 1
LCD control register L2 L23 L22 L21 L20 P23/SEG19 pin function switch bit P22/SEG18 pin function switch bit P21/SEG17 pin function switch bit P20/SEG16 pin function switch bit 0 1 0 1 0 1 0 1
at reset : 11112 SEG19 P23 SEG18 P22 SEG17 P21 SEG16 P20
at power down : state retained
W
Note: "R" represents read enabled, and "W" represents write enabled.
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FUNCTIONAL BLOCK OPERATIONS
1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 8) in RAM. 1 frame (2/F) M (1, 2, 8) COM0 COM1 1/F COM1 COM0 SEG16
COM1 SEG16 COM0 SEG16
0 (bit 0) 1 X X (bit 3)
Voltage level
VLC3 VLC1=VLC2 VSS
SEG16
VLC3 VLC1=VLC2 VSS
ON 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 8) in RAM.
OFF
1 frame (3/F) M (1, 2, 8) COM0 COM1 COM2 1/F COM2
Voltage level
1 (bit 0) 0 1 X (bit 3)
COM1
VLC3 VLC2 VLC1 VSS
SEG16 COM0 VLC3 VLC2 VLC1 VSS
SEG16
COM2 SEG16 COM1 SEG16 COM0 SEG16
ON
OFF
ON
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 8) in RAM. 1 frame (4/F) M (1, 2, 8) COM0 COM1 COM2 COM3 SEG16 COM1 1/F COM3
Voltage level
0 (bit 0) 1 0 1 (bit 3)
COM2
VLC3 VLC2 VLC1 VSS
COM0 VLC3 VLC2 VLC1 VSS
F: LCD clock frequency X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.)
SEG16
COM3 SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16
ON
OFF
ON
OFF
Fig. 27 LCD controller/driver structure
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
RESET FUNCTION
____________
System reset is performed by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied;
* the value of supply voltage is the minimum value or more of the recommended operating conditions. ____________ Then when "H" level is applied to RESET pin, software starts from address 0 in page 0.
f(XIN)
RESET
"H" "L"
(Note) f(XIN) is counted 10757 to 10786 times
Software start (Address 0 in page 0)
Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed.
Fig. 28 Reset release timing
Reset input 1machine cycle or more
f(XIN) is counted 10757 to 10786 times
=
0.85VDD RESET 0.3VDD (Note)
Software start (Address 0 in page 0)
Note: Keep the value of supply voltage the minimum value or more of the recommended operating conditions.
Fig. 29 RESET pin input waveform and reset operation (1) Power-on reset Reset can be automatically performed at power on (poweron reset) by the built-in power-on reset circuit. When the builtin power-on reset circuit is used, the time for the supply voltage to reach the minimum operating voltage must be set to 100
s or less. If the rising time exceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
VDD
Pull-up transistor
RESET pin
Power-on reset circuit
Internal reset signal
Power-on reset circuit output voltage
Voltage drop detection circuit (Note)
Reset state
Watchdog timer output WEF Internal reset signal
Note:
This symbol represents a parasitic diode. Applied potential to RESET pin must Power-on be VDD or less.
Reset released
Fig. 30 Power-on reset circuit example
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FUNCTIONAL BLOCK OPERATIONS
(2) Internal state at reset Table 14 shows port state at reset, and Figure 31 shows internal state at reset (they are retained after system is released from reset). Table 14 Port state at reset Name D0-D4, D5/INT D6/XCIN, D7/XCOUT P00-P03 P10-P13 P20/SEG16-P23/SEG19 SEG0-SEG15 COM0-COM3 CARR Function D0-D4, D5 D6, D7 P00-P03 P10-P13 P20-P23 SEG0-SEG15 COM0-COM3 CARR
The contents of timers, registers, flags and RAM except those shown in Figure 31 are undefined, so set the initial values to them.
State High impedance (Note 1) "H" (VDD) level (Note 1) (Notes 1, 2) High impedance VLC3 (VDD) level "L" (VSS) level
Notes 1: Output latch is set to "1." 2: The pull-up transistor is turned off.
* Program counter (PC) ............................................................................................ 000000 Address 0 in page 0 is set to program counter. 0 * Interrupt enable flag (INTE) ................................................................................... * Power down flag (P) ............................................................................................... 0 * External 0 interrupt request flag (EXF0) ................................................................ 0 0000 * Interrupt control register V1 ................................................................................... * Interrupt control register I1 .................................................................................... 0000 0 * Timer 1 interrupt request flag (T1F) ...................................................................... 0 * Timer 2 interrupt request flag (T2F) ...................................................................... * Watchdog timer flag (WDF) ................................................................................... 0 0 * Watchdog timer enable flag (WEF) ....................................................................... 0000 * Timer control register W1 ...................................................................................... * Timer control register W2 ...................................................................................... 0000 00 * Timer control register W3 ...................................................................................... 1000 * Clock control register MR ...................................................................................... * Carrier wave selection register C1 ........................................................................ 0111 0 * Carrier wave output control register C2 ................................................................. 0 * Carrier wave generating control flag CR ............................................................... * LCD control register L1 .......................................................................................... 0000 1111 * LCD control register L2 .......................................................................................... 0000 * Pull-up control register PU0 ................................................................................... * General-purpose register V2 ................................................................................. 0000 0 * Carry flag (CY) ....................................................................................................... 0000 * Register A .............................................................................................................. * Register B .............................................................................................................. 0000 !!! * Register D .............................................................................................................. * Register E .............................................................................................................. !!!!!!!! * Data pointer X ........................................................................................................ 0000 0000 * Data pointer Y ........................................................................................................ !! * Data pointer Z ........................................................................................................ * Stack pointer (SP) .................................................................................................. 111
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled)
(Prescaler stopped) (Timer 1 stopped) (Timer LC stopped)
(Carrier wave output disabled) (LCD off) (Port P2 selected)
"!" represents undefined.
Fig. 31 Internal state at reset
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value.
Pull-up transistor
RESET pin
Power-on reset circuit
Internal reset signal
Voltage drop detection circuit
Watchdog timer output
WEF
Fig. 32 Voltage drop detection reset circuit
VDD
Reset voltage
The microcomputer starts operation after the f(XIN) is counted 10757 to 10786 times.
Internal reset signal
Fig. 33 Voltage drop detection circuit operation waveform
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FUNCTIONAL BLOCK OPERATIONS
POWER DOWN FUNCTION
The 4551 Group has 2-type power down functions. q Clock operating mode ................................... POF instruction q RAM back-up mode .................................... POF2 instruction Power down is performed by executing each instruction. Above power down functions are different from reset in start conditions. Table 15 shows the function and states retained at power down. Figure 36 shows the state transition. q Return from power down state ............. Warm start condition q Return from reset state ........................... Cold start condition (1) Clock operating mode The following functions and states are retained. q RAM q Reset circuit q XCIN-XCOUT oscillation q LCD display q Timer 2 (2) RAM back-up mode The following functions and states are retained. q RAM q Reset circuit Unlike the clock operating mode, all oscillations stop in the RAM back-up mode. (3) Warm start condition The system returns from the power down state when; q the external wakeup signal is input or the timer 2 underflow occurs in the clock operating mode, or when; q the external wakeup signal is input in the RAM back-up mode. In either case, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is "1." (4) Cold start condition The CPU starts executing the software from address 0 in page 0 when; q reset pulse is input to RESET pin, q reset by watchdog timer is performed, or q reset by the voltage drop detection circuit is performed. In this case, the P flag is "0."
Table 15 Functions and states retained at power down Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Clock control register MR Timer control register W1 Timer control registers W2, W3 Interrupt control register V1 Interrupt control register I1 Carrier wave control registers and flag (C1, C2, CR) LCD display function LCD control registers L1, L2 Timer LC Timer 1 function Timer 2 function External 0 interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Watchdog timer flag (WDF) Watchdog timer enable flag (WEF) Interrupt enable flag (INTE) Power down Clock RAM operating back-up ! O O O ! O ! O ! O O O ! O ! ! O O O ! ! ! O O O ! O ! O ! (Note 3) O (Note 4) ! O ! ! O ! O ! !
General-purpose register V2 Notes 1: "O" represents that the function can be retained, and "!" represents that the function is initialized. Registers and flags other than the above are undefined at power down, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "1112" at power down. 3: LCD is turned off. 4: The state of the timer is undefined.
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(5) Identification of the start condition Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. The warm start condition (timer 2 or external wakeup signal) can be identified by examining the state of T2F flag.
Software start P = "1" ?
R
POF instruction or POF2 instruction Reset input
Powerdown flag P S Q
Yes
No Cold start
Yes
T2F = "1" ? No
q Set source q Clear source
POF or POF2 instruction executed Reset input
Return by timer 2 underflow
Return by external wakeup signal
Fig. 34 Set source and clear source of the P flag (6) Return signal An external wakeup signal or timer 2 interrupt request flag is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 16 shows the return condition for each return source.
Fig. 35 Start condition identified example using the SNZP instruction (7) Port P1 control register q Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P1 pull-up transistor and the ON/OFF of the key-on wakeup function. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. Remarks
Table 16 Return source and return condition Return source External wakeup signal Return condition Ports P0, P1 Returns by an external falling Port P0 shares the falling edge detection circuit with port P1. The key-on edge input ("H""L"). wakeup function of port P0 is always valid. The only key-on wakeup function of the port P1 bit of which the pull-up transistor is turned on is valid. Set all the port using the key-on wakeup function to "H" level before going into the power down state.
Timer 2 interrupt Returns by timer 2 underflow and The timer 2 interrupt request flag (T2F) can be used only when system setting T2F to "1." returns from the clock operating mode (POF instruction execution). request flag However, if the POF and POF2 instructions are executed while the T2F = "1", its operation is recognized as the return condition and system returns from the clock operating mode. Note: P1 pin has the pull-up transistor which can be turned on/off by software. Table 17 Pull-up control register Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor 0 1 0 1 0 1 at reset : 00002 at power down : state retained R/W
Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup
0 Pull-up transistor ON, key-on wakeup control bit 1 Note: "R" represents read enabled, and "W" represents write enabled.
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(8) State transition State transition is described using Figure 36.
Reset
POF execution
A,E
Return input 1
I
Clock operating mode
f(XCIN):Stop
A
f(XIN):Oscillation f(XCIN):Stop System clock; f(XIN)/4 MR=(10002)
(Stabilizing time d )
E
MR3 1 MR3 0
(Note 2)
POF2 execution
f(XIN):Oscillation f(XCIN):Stop System clock; f(XIN) MR=(00002)
(Stabilizing time d )
K
A,E
Return input 1
A,E
A,E
(Stabilizing time a )
(Stabilizing time a ) f(XIN):Stop
POF execution
B,F
Return input 1, 2
J
Clock operating mode
f(XIN):Stop f(XCIN) : Oscillation
B
0 M 0 MRR2 R2 3 2 0 MMR 1 (Note 2) M 1 MRR3 3 2 1 ) 1 MRR3 ime d (Stab 0 t iliz M in ing
( ab St iliz
MR2 1
MR2 0
MR2 1
MR2 0
gt
im
e
f(XIN):Oscillation f(XCIN):Oscillation System clock; f(XIN)/4 MR=(11002)
MR3 1 MR3 0
(Note 2)
d)
F
f(XIN):Oscillation f(XCIN):Oscillation System clock; f(XIN) MR=(01002)
RAM back-up mode
f(XIN):Stop f(XCIN):Stop
POF2 execution
B,F
Return input 1
B,F
(Stabilizing time a )
B,F
(Stabilizing time a )
POF execution
C
f(XIN):Oscillation f(XCIN):Oscillation System clock; f(XCIN)/4 MR=(11012)
(Stabilizing time c )
M 1 0 MRR0 R0 3 M R0 0 M 1 1 MR 3 0 M 0 MR 3 (Note 2) R3 1 MR 0
MR3 1 MR3 0
MR0 0
MR0 1
MR0 1
MR0 0
(Note 2)
C,G
Return input 1, 2
G
f(XIN):Oscillation f(XCIN):Oscillation System clock; f(XCIN) MR=(01012)
(Stabilizing time c )
c)
POF2 execution
C,G
Return input 1
C,G
(Stabilizing time c ) (Note 1)
MR1 0
MR1 1
MR1 1
tim
e
POF execution
D,H
Return input 1, 2
D
f(XIN):Stop f(XCIN):Oscillation System clock; f(XCIN)/4 MR=(11112)
1 1 MR 3 MR
1
c)
(St
ab
iliz
M MR R1 3 1 0
MR1 0
M MRR1 (S 3 tab 0 iliz ing 1
C,G
(Stabilizing time b )
0 0 R1 3 me MR ti M ing
POF2 execution
H
f(XIN):Stop f(XCIN):Oscillation System clock; f(XCIN) MR=(01112)
MR3 1 MR3 0
D,H
Return input 1
D,H
(Stabilizing time c ) (Note 1)
D,H
(Stabilizing time b )
Stabilizing time a : An interval required to stabilize the f(XIN) oscillation is automatically generated by hardware. Stabilizing time b : An interval required to stabilize the f(XCIN) oscillation is automatically generated by hardware. Stabilizing time c : Generate an interval required to stabilize the f(XIN) oscillation in state C or G by software at the transition DC, DG, HC, HG, JC, or JG. Stabilizing time d : Generate an interval required to stabilize the f(XCIN) oscillation in state B, F by software at the transition AB, EF, AF, or EB. Return input 1: External wakeup signal (P00-P03, P10-P13) Return input 2: Timer 2 interrupt request flag Notes 1. MR3="1"The microcomputer starts its operation after counting f(XCIN) clock signal 59 to 70 times. MR3="0"The microcomputer starts its operation after counting f(XCIN) clock signal 32 to 43 times. 2. When the following 2 conditions are satisfied, the transition AE, BF, AF, CF, GF represented by " " can be executed. (1) VDD = 2.2 V to 5.5 V (One Time PROM version: VDD = 2.5 V to 5.5 V), f(XIN) 1.0 MHz (2) VDD = 4.5 V to 5.5 V, f(XIN) 2.0 MHz
Fig. 36 State transition
4551 Group User's Manual
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS
CLOCK CONTROL
The clock control circuit consists of the following circuits. q Clock generating circuit q Control circuit to stop the clock oscillation q System clock (STCK) selection circuit q Instruction clock (INSTCK) generating circuit q Control circuit to return from the power down state
MR0
XIN XOUT
OSC
Multiplexer
Frequency dividing circuit (divided by 4)
MR3
Internal clock 1 0 generating circuit (divided by 3)
INSTCK
STCK
XCIN XCOUT
POF instruction R S POF2 instruction R S Q Q
MR1
OSC
RESET T2F flag
Falling detected
Fig. 37 Clock control circuit structure (1) Clock control register q Clock control register MR Register MR controls the system clock. Set the contents of this register through register A with the TMRA Table 18 Clock control register Clock control register MR 0 MR3 System clock (STCK) selection bit 1 MR2 MR1 MR0 f(XCIN) oscillation circuit control bit f(XIN) oscillation circuit control bit Clock selection bit 0 1 0 1 at reset : 10002 MR0=0 f(XIN) MR0=1 f(XCIN) MR0=0 f(XIN)/4
Ports P0, P1
instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A.
at power down : state retained
R/W
MR0=1 f(XCIN)/4 f(XCIN) oscillation stop, ports D6 and D7 selected f(XCIN) oscillation enabled, ports D6 and D7 not selected Oscillation enabled Oscillation stop
f(XIN) 0 f(XCIN) 1 Note: "R" represents read enabled, and "W" represents write enabled.
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HARDWARE
FUNCTIONAL BLOCK OPERATIONS/ROM ORDERING METHOD
(2) f(XIN) clock generating circuit Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. (3) f(XCIN) clock generating circuit Clock signal f(XCIN) is obtained by externally connecting a quartz-crystal oscillator. Connect this external circuit to pins XCIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT.
M34551
XIN
CIN
Note: Externally connect a damping resistor Rd depending on the XOUT oscillation frequency. (A feedback resistor is built-in.) Rd Use the resonator manufacturer's recommended value COUT because constants such as capacitance depend on the resonator.
ROM ORDERING METHOD
Please submit the information described below when ordering Mask ROM. (1) M34551M4-XXXFP Mask ROM Order Confirmation Form ..............................................................................................1 (2) Data to be written into mask ROM * EPROM (three sets containing the identical data) (3) Mark Specification Form .................................................... 1 Fig. 38 Ceramic resonator external circuit
M34551 XCIN
CIN
Note: Externally connect a damping resistor Rd depending on the XCOUT oscillation frequency. (A feedback resistor is built-in.) Rd Use the quartz-crystal oscillator manufacturer's recommended value COUT because constants such as capacitance depend on the quartz-crystal oscillator.
Fig. 39 Quartz-crystal oscillator external circuit
4551 Group User's Manual
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HARDWARE
LIST OF PRECAUTIONS
LIST OF PRECAUTIONS
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use the thickest wire. In the built-in PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k (connect this resistor to CNVSS/ VPP pin as close as possible).
* Use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output autocontrol function is selected. If the ORCLK is used as the count source, a hazard may occur in port CARR output because ORCLK is not synchronized with the carrier wave. * When "no carrier wave" is selected with register C1 ((C13C12C11C10) = (0101), (1101)), the enable/disable of the carrier wave output cannot be controlled by the carrier wave output auto-control function.
D5/INT pin
When the interrupt valid waveform of D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Clear the bit 0 of register V1 to "0" and then change the interrupt valid waveform of D5/INT pin with the bit 2 of register I1 (refer to Figure 40). * Clear the bit 2 of register I1 to "0" and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 40). Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. . . . LA TV1A LA TI1A NOP SNZ0 NOP . . . 4 ; Change of the interrupt valid waveform
Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
Count source
Stop timer 1 or timer LC counting to change its count source. When timer 2 count source changes from f(XCIN) to ORCLK (W23 = "0" W23 = "1"), the count value of timer 2 is initialized. However, when timer 2 count source changes from ORCLK to f(XCIN) (W23 = "1" W23 = "0") or the same count source is set again (W23 = "0" W23 = "0" or W23 = "1" W23 = "1"), the count value of timer 2 is not initialized.
Timer 2
Timer 2 has the watchdog timer function (WDT). When timer 2 is used as the WDT, note that the processing to initialize the count value and the execution of the WRST instruction.
4
; (!!!02) ; The SNZ0 instruction is valid
Reading the count value
Stop the prescaler and then execute the TAB1 instruction to read timer 1 data.
;The SNZ0 instruction is executed ! : this bit is not related to the setting of INT.
Writing to reload register R1
Write the data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
Fig. 40 External 0 interrupt program example
Notes when using the carrier wave output auto-control function
* Execute the STCR instruction after setting the timer 1 and register C2 in order to start the carrier generating circuit operation. * Stop the timer 1 (W20="0") after stopping the carrier generating circuit (SPCR instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. * If the carrier wave output auto-control function is invalidated (C20="0") while the carrier wave output is auto-controlled, the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This state is released by timer 1 stop (W20="0"). When the carrier wave output auto-control function is validated (C20="1") again after it is invalidated (C20="0"), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur.
One Time PROM version
The operating power voltage of the One Time PROM version is within the range of 2.5 V to 5.5 V.
Multifunction
Note that the port D5 output function can be used even when INT function is selected.
11
Power down instruction (POF instruction, POF2 instruction) Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the power down state. Note that system cannot enter the power down state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instrcution. counter Make sure that the PCH does not specify after the last page of the built-in ROM.
12 Program
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4551 Group User's Manual
HARDWARE
SYMBOL
SYMBOL
The symbols shown below are used in the following list of instruction function and machine instructions. Symbol A B DR E V1 V2 I1 W1 W2 W3 C1 C2 CR L1 L2 PU0 MR X Y Z DP PC PCH PCL SK SP CY R1 R2 RLC STCK INSTK T1 T2 TLC Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) General-purpose register V2 (4 bits) Interrupt control register I1 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (2 bits) Carrier wave selection register C1 (4 bits) Carrier wave output control register C2 (1 bit) Carrier wave generating control flag LCD control regiser L1 LCD control register L2 Pull-up control register PU0 (4 bits) Clock control register MR (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ! 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer LC reload register System clock Instruction clock Timer 1 Timer 2 Timer LC A3A2A1A0 D P0 P1 P2 x y z p n i j Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) Contents Symbol WDF INTE EXF0 P Contents Watchdog timer flag Interrupt enable flag External 0 interrupt request flag Power down flag
? () -- M(DP) a p, a C +
x Timer 1 interrupt request flag T1F Timer 2 interrupt request flag T2F Note : The 4551 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
4551 Group User's Manual
1-41
HARDWARE
LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION
Grouping
Mnemonic TAB TBA TAY TYA TEAB
Function (A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B)
Grouping
RAM to register transfer
(Y) (Y) + 1 TMA j (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 LA n (A) n n = 0 to 15
Bit operation
Function Mnemonic (A) (M(DP)) XAMI j (X) (X)EXOR(j) j = 0 to 15
Grouping
Mnemonic SB j
Function (Mj(DP)) 1 j = 0 to 3
RB j
(Mj(DP)) 0 j = 0 to 3
SZB j
(Mj(DP)) = 0 ? j = 0 to 3
Register to register transfer
TABE
(B) (E7-E4) (A) (E3-E0) TABP p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7 to 4 (A) (ROM(PC))3 to 0 (PC) (SK(SP)) (SP) (SP) - 1 AM Arithmetic operation AMC (A) (A) + (M(DP))
Comparison operation
(E3-E0) (A)
SEAM SEA n
(A) = (M(DP)) ? (A) = n ? n = 0 to 15
TDA TAD
(DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x, x = 0 to 15 (Y) y, y = 0 to 15 (Z) z, z = 0 to 3 AND
Ba Branch operation BL p, a
(PCL) a6-a0 (PCH) p (PCL) a6-a0 (PCH) p (PCL) (DR2-DR0, A3-A0)
TAZ
BLA p
TAX TASP
BM a (A) (A) + (M(DP)) + (CY) (CY) Carry An (A) (A) + n n = 0 to 15 (A) (A)AND(M(DP)) (A) (A)OR(M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 RTI Subroutine operation
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0
LXY x, y RAM addresses
BML p, a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 BMLA p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (PC) (SK(SP)) (SP) (SP) - 1
LZ z INY DEY TAM j
(Y) (Y) + 1 OR (Y) (Y) - 1 SC (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 RC SZC
RAM to register transfer
XAM j
(A) (M(DP)) Return operation (X) (X)EXOR(j) j = 0 to 15 RAR CMA RT
(PC) (SK(SP)) (SP) (SP) - 1
XAMD j
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
RTS
(PC) (SK(SP)) (SP) (SP) - 1
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4551 Group User's Manual
HARDWARE
LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Grouping
Mnemonic DI EI SNZ0
Function (INTE) 0 (INTE) 1
Grouping
Mnemonic TLCA
Function (TLC) (A) (RLC) (A) (T1F) = 1 ? After skipping the next instruction, (T1F) 0
Grouping Mnemonic
Carrier wave generating operation
TC1A STCR
Function (C1) (A) Carrier wave generating start Carrier wave generating stop (C20) (A0)
SNZT1 (EXF0) = 1 ? After skipping the next Interrupt operation instruction, (EXF0) 0 SNZI0 I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ? (A) (V1) IAP0 TV1A TAI1 TI1A TAW1 TW1A TAW2 TW2A TAW3 TW3A TAB1 (V1) (A) OP0A (A) (I1) IAP1 (I1) (A) OP1A (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A1, A0) (W31, W30) (W31, W30) (A1, A0) TPU0A Timer operation (B) (T17-T14) (A) (T13-T10) T1AB at timer 1 stop (W20=0) LCD control operation (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) At timer 1 operating (W20=1), (R17-R14) (B) (R13-R10) (A) TAPU0 TL1A TAL1 TL2A Input/Output operation IAP2 CLD RD Timer operation
SPCR
SNZT2
(T2F) = 1 ? After skipping the next instruction, (T2F) 0
TC2A
NOP POF
(PC) (PC) + 1 Transition to clock operating mode
TAV1
(A) (P0) (P0) (A)
POF2 (A) (P1) (P1) (A) Other operation (A) (P2) (D) 1 (D(Y)) 0 (Y) = 0 to 7 SD (D(Y)) 1 (Y) = 0 to 7 TAV2 (PU0) (A) TV2A (A) (PU0) (L1) (A) (A) (L1) (L2) (A) TAMR TMRA EPOF
Transition to RAM back-up mode Power down instruction (POF, POF2) valid
SNZP WRST
(P) = 1 ? (WDF) 0, (WEF) 1 (A) (MR) (MR) (A) (A) (V2) (V2) (A)
4551 Group User's Manual
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HARDWARE
INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE
D9-D4 000000 000001 000010 000011 000100 000101000110 000111001000001001 001010 001011 001100 001101001110 001111 D3- D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Hex. notation
010000 011000 010111 011111
00 NOP - POF
01 BLA CLD -
02
03
04 - - - - RT
05 TASP TAD TAX TAZ TAV1
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D
0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
10-17 18-1F
0 1 2 3 4 5 6 7 8 9 A B C D E F
SZB BMLA 0 SZB 1 SZB 2 SZB 3 - - - - - - - - SNZ0 -
TABP TABP TABP TABP 0 16 32* 48* BML BML TABP TABP TABP TABP BML BML 1 17 33* 49* TABP TABP TABP TABP BML BML 2 18 34* 50* TABP TABP TABP TABP BML BML 3 19 35* 51* TABP TABP TABP TABP 4 20 36* 52* BML BML TABP TABP TABP TABP 5 21 37* 53* BML BML TABP TABP TABP TABP BML 6 22 38* 54* BML TABP TABP TABP TABP 7 23 39* 55* BML BML TABP TABP TABP TABP 8 40* 56* BML BML 24 TABP TABP TABP TABP BML BML 9 25 41* 57* TABP TABP TABP TABP 10 42* 58* BML BML 26 TABP TABP TABP TABP 11 43* 59* BML BML 27 TABP TABP TABP TABP 12 28 44* 60* BML BML TABP TABP TABP TABP BML BML 13 29 45* 61* TABP TABP TABP TABP BML BML 14 30 46* 62* TABP TABP TABP TABP 15 31 47* 63* BML BML
BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM
B B B B B B B B B B B B B B B B
SNZP INY DI EI RC SC RD
SD SEAn - DEY SEAM - - TDA
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
POF2 AND - OR
AM TEAB TABE SNZI0 AMC - - - - - - - - TV2A
TYA CMA - TBA - RAR TAB TAY
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D 3-D0 show the low-order 4 bits of the machine language code, and D 9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. * cannot be used at M34551M4. The second word BL BML BLA BMLA SEA 10 10 10 10 00 paaa paaa pp00 pp00 0111 aaaa aaaa pppp pppp nnnn
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4551 Group User's Manual
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INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (CONTINUED)
D9-D4 100000 100001100010 100011100100 100101100110 100111101000 101001101010 101011101100 101101101110 101111 D3- D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Hex. notation
110000 111111
20 - - - - - - - - - - TL1A TL2A - TLCA TW1A TW2A
21
22
23
24 - - - - - - - - - - TAL1 TAW1 TAW2 TAW3 - -
25 - -
26
27
28
29 - - - - - - - -
2A WRST - - - - - - -
2B
2C
2D
2E
2F
30-3F
0 1 2 3 4 5 6 7 8 9 A B C D E F
TW3A OP0A T1AB - - - - - TMRA TI1A - - - - - - - - OP1A - - - - - - - - - - -
TPU0A
IAP0 TAB1 SNZT1 IAP1 - - - - - - - - - - - - - - -
SNZT2
TMA TAM XAM XAMI XAMD LXY 0 0 0 0 0 TMA TAM XAM XAMI XAMD LXY 1 1 1 1 1 TMA TAM XAM XAMI XAMD LXY 2 2 2 2 2 TMA TAM XAM XAMI XAMD LXY 3 3 3 3 3 TMA TAM XAM XAMI XAMD LXY 4 4 4 4 4 TMA TAM XAM XAMI XAMD LXY 5 5 5 5 5 TMA TAM XAM XAMI XAMD LXY 6 6 6 6 6 TMA TAM XAM XAMI XAMD LXY 7 7 7 7 7 TMA TAM XAM XAMI XAMD LXY 8 8 8 8 8 TMA TAM XAM XAMI XAMD LXY 9 9 9 9 9 TMA TAM XAM XAMI XAMD LXY 10 10 10 10 10 TMA TAM XAM XAMI XAMD LXY 11 11 11 11 11 TMA TAM XAM XAMI XAMD LXY 12 12 12 12 12 TMA TAM XAM XAMI XAMD LXY 13 13 13 13 13 TMA TAM XAM XAMI XAMD LXY 14 14 14 14 14 TMA TAM XAM XAMI XAMD LXY 15 15 15 15 15
- - - - - - - - - - - - - - -
TAMR IAP2 TAI1 - - -
TAPU0
- - - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - -
STCR TC1A SPCR TC2A - - - - - - - - - - - -
- -
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word BL BML BLA BMLA SEA 10 10 10 10 00 paaa paaa pp00 pp00 0111 aaaa aaaa pppp pppp nnnn
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS
Parameter
Type of instructions
Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal notation
Number of words Number of cycles
Function
TAB TBA TAY TYA TEAB Register to register transfer
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
1 0 1 0 1
1 1 1 1 1
1 1 1 1 0
1 1 1 0 1
0 0 1 0 0
0 0 0 0 0
1 0 1 0 1
E E F C A
1 1 1 1 1
1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) (E7-E4) (A) (E3-E0)
TDA TAD
0 0
0 0
0 0
0 1
1 0
0 1
1 0
0 0
0 0
1 1
0 0
2 5
9 1
1 1
1 1
(DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) (Z1, Z0) (A3, A2) 0
TAX TASP
0 0
0 0
0 0
1 1
0 0
1 1
0 0
0 0
1 0
0 0
0 0
5 5
2 0
1 1
1 1
(A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x, x = 0 to 15 (Y) y, y = 0 to 15
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
1
1
RAM addresses
LZ z
0
0
0
1
0
0
1
0
z1 z0
0
4
8 +z
1
1
(Z) z, z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0
1
3
1
1
(Y) (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0
1
7
1
1
(Y) (Y) - 1
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HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Detailed description
- - - - -
- - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E.
-
-
Transfers the contents of register E to registers A and B.
- -
- -
Transfers the contents of register A to register D. Transfers the contents of register D to register A.
-
-
Transfers the contents of register Z to register A.
- -
- -
Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to register A.
Continuous description
-
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped.
-
-
Loads the value z in the immediate field to register Z.
(Y) = 0
-
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.
(Y) = 15
-
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped.
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (CONTINUED)
Parameter
Type of instructions
Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal notation
Number of words Number of cycles
Function
TAM j
1
0
1
1
0
0
j
j
j
j
2C
j
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2D
j
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
RAM to register transfer
XAMD j
1
0
1
1
1
1
j
j
j
j
2F
j
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2E
j
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2B
j
1
1
(M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
LA n
0
0
0
1
1
1
n
n
n
n
07
n
1
1
(A) n n = 0 to 15
Arithmetic operation
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
08 +p
p
1
3
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7 to 4 (A) (ROM(PC))3 to 0 (PC) (SK(SP)) (SP) (SP) - 1 (Note)
Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551M8 and M34551E8.
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HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Detailed description
-
-
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
-
-
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
-
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped.
(Y) = 0
-
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.
-
-
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Continuous description
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
-
-
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, 1 stage of stack register is used.
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (CONTINUED)
Parameter
Type of instructions
Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal notation
Number of words Number of cycles
Function
AM
0
0
0
0
0
0
1
0
1
0
00A
1
1
(A) (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
00B
1
1
(A) (A) + (M(DP))+ (CY) (CY) Carry
An
0
0
0
1
1
0
n
n
n
n
06n
1
1
(A) (A) + n n = 0 to 15
Arithmetic operation
AND
0
0
0
0
0
1
1
0
0
0
018
1
1
(A) (A)AND(M(DP))
OR
0
0
0
0
0
1
1
0
0
1
019
1
1
(A) (A)OR(M(DP))
SC RC SZC CMA RAR SB j Bit operation
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 1 0 0 0
0 0 0 1 1 1
0 0 1 1 1 1
1 1 1 1 1 1
1 1 1 0 0 j
1 0 1 0 1 j
007 006 02F 01C 01D 05 C +j C +j j
1 1 1 1 1 1
1 1 1 1 1 1
(CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15
RB j
0
0
0
1
0
0
1
1
j
j
04
1
1
SZB j
0
0
0
0
1
0
0
0
j
j
02
1
1
Comparison operation
SEAM SEA n
0 0 0
0 0 0
0 0 0
0 0 1
1 1 1
0 0 1
0 0 n
1 1 n
1 0 n
0 1 n
02 02 07
6 5 n
1 2
1 2
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4551 Group User's Manual
HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Detailed description
-
-
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
-
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
-
Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation.
-
-
Performs the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
-
-
Performs the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A.
- - (CY) = 0 - - -
1 0 - -
Sets carry flag CY to "1." Clears carry flag CY to "0." Skips the next instruction when the contents of carry flag CY is "0." Stores the one's complement for register A's contents in register A.
0/1 Rotates the contents of register A including the contents of carry flag CY to the right by 1 bit. - Sets the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to "1."
-
-
Clears the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to "0."
(Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n
-
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
- -
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (CONTINUED)
Parameter
Type of instructions
Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal notation
Number of words Number of cycles
Function
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
18 a +a 0Ep +p 2p a +a 01 2p 1a 0 p a
1
1
(PCL) a6-a0
Branch operation
BL p, a
0
0
1
1
1
p4 p3 p2 p1 p0
2
2
(PCH) p (PCL) a6-a0 (Note)
1
0
p5 a6 a5 a4 a3 a2 a1 a0
BLA p
0 1
0 0 1
0
0
0
1 0
0
0
0
0
2
2
(PCH) p (PCL) (DR2-DR0, A3-A0) (Note)
p5 p4 0 0
p3 p2 p1 p0
BM a
0
a6 a5 a4 a3 a2 a1 a0
1
1
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0
Subroutine operation
BML p, a
0
0
1
1
0
p4 p3 p2 p1 p0
0Cp +p 2pa +a 03 2p 0 p
2
2
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 (Note)
1
0
p5 a6 a5 a4 a3 a2 a1 a0
BMLA p
0 1
0 0
0
0
1
1 0
0
0
0
0
2
2
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (Note)
p5 p4 0
p3 p2 p1 p0
RTI Return operation
0
0
0
1
0
0
0
1
1
0
04
6
1
1
(PC) (SK(SP)) (SP) (SP) - 1
RT
0
0
0
1
0
0
0
1
0
0
04
4
1
2
(PC) (SK(SP)) (SP) (SP) - 1
RTS
0
0
0
1
0
0
0
1
0
1
04
5
1
2
(PC) (SK(SP)) (SP) (SP) - 1
Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551M8 and M34551E8.
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HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Detailed description
-
-
Branch within a page : Branches to address a in the identical page.
-
-
Branch out of a page : Branches to address a in page p.
-
-
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
-
-
Returns from subroutine to the routine called the subroutine.
Skip unconditionally
-
Returns from subroutine to the routine called the subroutine, and skips the next instruction unconditionally.
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (CONTINUED)
Parameter
Type of instructions
Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal notation
Number of words Number of cycles
Function
DI EI SNZ0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
1 1 0
0 0 0
0 1 0
00 00 03
4 5 8
1 1 1
1 1 1
(INTE) 0 (INTE) 1 (EXF0) = 1 ? After skipping the next instruction, (EXF0) 0
Interrupt operation
SNZI0
0
0
0
0
1
1
1
0
1
0
03
A
1
1
I12 = 1 : (INT) = "H" ?
I12 = 0 : (INT) = "L" ?
TAV1 TV1A TAI1 TI1A SNZT1
0 0 1 1 1
0 0 0 0 0
0 0 0 0 1
1 0 1 0 0
0 1 0 0 0
1 1 1 1 0
0 1 0 0 0
1 1 0 1 0
0 1 1 1 0
0 1 1 1 0
054 03F 253 217 280
1 1 1 1 1
1 1 1 1 1
(A) (V1) (V1) (A) (A) (I1) (I1) (A) (T1F) = 1 ? After skipping the next instruction (T1F) 0
SNZT2
1
0
1
0
0
0
0
0
0
1
281
1
1
(T2F) = 1 ? After skipping the next instruction (T2F) 0
Timer operation
TAW1 TW1A TAW2 TW2A TAW3 TW3A
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
1 0 1 0 1 0
0 0 0 0 0 0
0 0 0 0 0 1
1 1 1 1 1 0
0 1 1 1 1 0
1 1 0 1 0 0
1 0 0 1 1 0
24B 20E 24C 20F 24D 210
1 1 1 1 1 1
1 1 1 1 1 1
(A) (W1) (W1) (A) (A) (W2) (W2) (A) (A1, A0) (W31, W30) (W31, W30) (A1, A0)
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MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Detailed description
- - (EXF0) = 1
- - -
Clears the interrupt enable flag INTE to "0," and disables the interrupt. Sets the interrupt enable flag INTE to "1," and enables the interrupt. Skips the next instruction when the contents of EXF0 flag is "1." After skipping, clears the EXF0 flag to "0."
(INT) = "H" However, I12 = 1 (INT) = "L" However, I12 = 0 - - - - (T1F) = 1
-
When bit 2 (I12) of register I1 is "1" : Skips the next instruction when the level of INT pin is "H."
-
When bit 2 (I12) of register I1 is "0" : Skips the next instruction when the level of INT pin is "L."
- - - - -
Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Skips the next instruction when the contents of T1F flag is "1." After skipping, clears T1F flag.
(T2F) =1
-
Skips the next instruction when the contents of T2F flag is "1." After skipping, clears T2F flag.
- - - - - -
- - - - - -
Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3.
4551 Group User's Manual
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (CONTINUED)
Parameter
Type of instructions
Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal notation
Number of words Number of cycles
Function
TAB1
1
0
0
1
1
1
0
0
0
0
270
1
1
(B) (T17-T14) (A) (T13-T10)
T1AB Timer operation
1
0
0
0
1
1
0
0
0
0
230
1
1
At timer 1 stop (W20=0), (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) At timer 1 operating (W20=1), (R17-R14) (B) (R13-R10) (A)
TLCA
1
0
0
0
0
0
1
1
0
1
20D
1
1
(TLC) (A) (RLC) (A)
IAP0 OP0A IAP1 OP1A Input/Output operation IAP2
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
1 0 1 0 1
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 1
0 0 1 1 0
260 220 261 221 262
1 1 1 1 1
1 1 1 1 1
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A) (P2)
CLD RD
0 0
0 0
0 0
0 0
0 0
1 1
0 0
0 1
0 0
1 0
011 014
1 1
1 1
(D) 1 (D(Y)) 0 (Y) = 0 to 7 (D(Y)) 1 (Y) = 0 to 7 (PU0) (A) (A) (PU0)
SD
0
0
0
0
0
1
0
1
0
1
015
1
1
TPU0A TAPU0
1 1
0 0
0 0
0 1
1 0
0 1
1 0
1 1
0 1
1 1
22D 257
1 1
1 1
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4551 Group User's Manual
HARDWARE
MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Detailed description
-
-
Transfers the contents of timer 1 to registers A and B.
-
-
When stopping (W20=0), transfers the contents of registers A and B to timer 1 and timer 1 reload register. When operating (W20=1), transfers the contents of registers A and B only to timer 1 reload register.
-
-
Transfers the contents of register A to timer LC and timer LC reload register.
- - - - -
- - - - -
Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A.
- -
- -
Sets port D to "1." Clears a bit of port D specified by register Y to "0."
-
-
Sets a bit of port D specified by register Y to "1."
- -
- -
Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU0 to register A.
4551 Group User's Manual
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HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (CONTINUED)
Parameter
Type of instructions
Instruction code Mnemonic D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal notation
Number of words Number of cycles
Function
TL1A LCD control operation TAL1 TL2A TC1A STCR SPCR TC2A NOP POF
1 1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 0 0
0 1 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0 0
0 0 0 0 1 1 0 0 0
1 1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 1
0 0 1 0 0 1 1 0 0
20A 24A 20B 2A8 298 299 2A9 000 002
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
(L1) (A) (A) (L1) (L2) (A) (C1) (A) Carrier wave generating start Carrier wave generating stop (C20) (A0) (PC) (PC) + 1 Transition to clock operating mode
Carrier generating circuit operation
POF2
0
0
0
0
0
0
1
0
0
0
008
1
1
Transition to RAM back-up mode
EPOF Other operation
0
0
0
1
0
1
1
0
1
1
0
5B
1
1
Power down instruction (POF, POF2) valid
SNZP
0
0
0
0
0
0
0
0
1
1
003
1
1
(P) = 1 ?
WRST TAMR TMRA TAV2 TV2A
1 1 1 0 0
0 0 0 0 0
1 0 0 0 0
0 1 0 1 0
1 0 0 0 1
0 1 1 1 1
0 0 0 0 1
0 0 1 1 1
0 1 1 0 1
0 0 0 1 0
2A0 252 216 055 03E
1 1 1 1 1
1 1 1 1 1
(WDF) 0, (WEF) 1 (A) (MR) (MR) (A) (A) (V2) (V2) (A)
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MACHINE INSTRUCTIONS
Skip condition
Carry flag CY
Detailed description
- - - - - - - - -
- - - - - - - - -
Transfers the contents of register A to LCD control register L1. Transfers the contents of register L1 to register A. Transfers the contents of register A to LCD control register L2. Transfers the contents of register A to carrier wave selection register C1. Starts generating carrier wave. Stops generating carrier wave. Transfers the contents of register A to carrier wave output control register C2. No operation Puts the system in clock operating mode state by executing the POF instruction after executing the EPOF instruction. f(XCIN) oscillation, LCD, timer LC and timer 2 are operated.
-
-
Puts the system in RAM back-up mode state by executing the POF2 instruction after executing the EPOF instruction. Oscillation is stopped.
-
-
Validates the power down instruction (POF, POF2) which is executed after the EPOF instruction by executing the EPOF instruction.
(P) = 1
-
Skips the next instruction when P flag is "1." After skipping, P flag remains unchanged.
- - - - -
- - - - -
Operates the watchdog timer and initializes the watchdog timer flag (WDF). Transfers the contents of clock control register MR to register A. Transfers the contents of register A to clock control register MR. Transfers the contents of general-purpose register V2 to register A. Transfers the contents of register A to general-purpose register V2.
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HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid)
Timer control register W1 W13 W12 Prescaler control bit Prescaler dividing ratio selection bit 0 1 0 1
at reset : 00002
at power down : 00002
R/W
Stop (prescaler state initialized) Operating Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 8 Count source 0
W11 W10
W11 Timer 1 count source selection bits W10
0 0 1 1
Prescaler output (ORCLK) 1 0 Carrier output (CARRY) 1 Carrier output divided by 2 (CARRY/2)
Timer control register W2 W23 Timer 2 count source selection bit 0 1
at reset : 10002 f(XCIN)
at power down : - - - 02
R/W
Prescaler output (ORCLK) Count source Underflow occur every 214 count Underflow occur every 213 count Not available Not available Stop (timer 1 state retained) Operating 0 1 0 1
W22 W21
W22 Timer 2 count value selection bits W21
0 0 1 1 Timer 1 control bit 0 1
W20
Timer control register W3 W31 Timer LC count source selection bit 0 1
at reset : 002
at power down : state retained
R/W
Bit 3 of timer 2 is output (timer 2 count source divided by 16) System clock (STCK)
0 Stop (timer LC state retained) Timer LC control bit W30 1 Operating Note: "R" represents read enabled, and "W" represents write enabled. "-" represents state retained.
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HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS (CONTINUED)
Interrupt control register I1 I13 Not used 0 1 0 I12 Interrupt valid waveform for INT pin selection bit (Note 2) 1 0 1 0 1 at reset : 00002 at power down : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction) Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)
I11 I10
Not used Not used
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W
Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup
Clock control register MR 0 MR3 System clock (STCK) selection bit 1 MR2 MR1 MR0 f(XCIN) oscillation circuit control bit f(XIN) oscillation circuit control bit Clock selection bit 0 1 0 1
at reset : 10002 MR0=0 f(XIN) MR0=1 f(XCIN) MR0=0 f(XIN)/4
at power down : state retained
R/W
MR0=1 f(XCIN)/4 f(XCIN) oscillation stop, ports D6 and D7 selected f(XCIN) oscillation enabled, ports D6 and D7 not selected Oscillation enabled Oscillation stop
f(XIN) 0 f(XCIN) 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to "1" when the contents of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction.
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HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS (CONTINUED)
Carrier wave selection register C1 at reset : 01112 C13 C12 C11 C10 0 0 0 0 0 0 0 Carrier wave selection bits 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at power down : 01112 Duty 1/3 1/2 1/4 1/2 1/2 W
Carrier wave frequency STCK/24 STCK/24 STCK/16 STCK/16 STCK/2 No carrier wave Not available "L" fixed STCK/12 STCK/12 STCK/8 STCK/8 STCK No carrier wave Not available "L" fixed 1/3 1/2 1/4 1/2 1/2
Carrier wave output control register C2 C20 Carrier wave output auto-control bit 0 1
at reset : 02
at power down : 02
W
Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid
Carrier wave generating control flag CR CR Carrier wave generating control 0 1
at reset : 02
at power down : 02
W
Carrier wave generating stop (SPCR instruction) Carrier wave generating start (STCR instruction)
Note: "W" represents write enabled.
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HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS (CONTINUED)
LCD control register L1 L13 L12 Not used LCD on/off bit 0 1 0 1
L11 L10
at reset : 00002
at power down : state retained
R/W
This bit has no function, but read/write is enabled Off On Duty Not available 1/2 1/3 1/4 1/2 1/3 1/3 Bias 0 1 0 1
L11 LCD duty and bias selection bits L10
0 0 1 1
LCD control register L2 L23 L22 L21 L20 P23/SEG19 pin function switch bit P22/SEG18 pin function switch bit P21/SEG17 pin function switch bit P20/SEG16 pin function switch bit 0 1 0 1 0 1 0 1
at reset : 11112 SEG19 P23 SEG18 P22 SEG17 P21 SEG16 P20
at power down : state retained
W
General-purpose register V2 4-bit general-purpose register.
at reset : 00002
at power down : 00002
R/W
The data transfer between register A and this register is performed with the TV2A and TAV2 instructions. Note: "R" represents read enabled, and "W" represents write enabled.
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HARDWARE
BUILT-IN PROM VERSION
BUILT-IN PROM VERSION
In addition to the mask ROM version, the 4551 Group has the programmable ROM version software compatible with mask ROM. The One Time PROM version has PROM which can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM version, but it has a PROM mode that enables writing to built-in PROM. Table 19 Product of built-in PROM version Product M34551E8-XXXFP 8192 words M34551E8FP 280 words PROM size (! 10 bits) RAM size (! 4 bits)
Table 19 shows the product of built-in PROM version. Figure 41 shows the pin configurations of built-in PROM version. The One Time PROM version has pin-compatibility with the mask ROM version.
Package
ROM type One Time PROM [shipped after writing] (shipped after writing and test in factory) One Time PROM [shipped in blank]
48P6S-A
PIN CONFIGURATION (TOP VIEW)
SEG8 SEG3 COM2 SEG7 SEG2 COM1
27
37
SEG6
34
32
31
SEG1
38
36
35
33
29
28
26
COM0
SEG5
SEG0
SEG9 SEG10 SEG11 SEG12 VSS SEG13 SEG14 SEG15 P20 / SEG16 P21 / SEG17
30
25
RESET
SEG4
COM3
39 40 41 42 43 44 45 46 47 48
24 23 22 21
D7/XCOUT D6/XCIN CNVSS XOUT XIN VSS VDD CARR D5 / INT D4
M34551E8-XXXFP
20 19 18 17 16 15
10
11
12
P22 / SEG18
P23 / SEG19
P03
P02
P01
P00
P10
P11
P12
P13
D2
13
Outline 48P6S-A Fig. 41 Pin configuration of built-in PROM version
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D0
D1
D3
14
3
4
5
6
7
1
2
8
9
HARDWARE
BUILT-IN PROM VERSION
(1) PROM mode The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 20. Contact addresses at the end of this book for the appropriate PROM programmer. * Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 42. (2) Notes on handling A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. For the One Time PROM version shipped in blank, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 43 before using is recommended. ( Products shipped in blank: PROM contents is not written in factory when shipped)
Table 20 Programming adapter Microcomputer M34551E8-XXXFP, M34551E8FP Programming adapter PCA7414
Address 000016 1FFF16
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
400016 5FFF16
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
7FFF16 Set "FF16" to the shaded area.
Fig. 42 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 C exceeding 100 hours.
Fig. 43 Flow of writing and test of the product shipped in blank
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HARDWARE
BUILT-IN PROM VERSION
MEMO
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4551 Group User's Manual
CHAPTER 2 APPLICATION
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 I/O pins Interrupts Timers Carrier generating circuit Liquid crystal display Power down function Reset Oscillation circuit
APPLICATION
2.1 I/O pins
2.1 I/O pins
The 4551 Group has the eight I/O pins, four input pins and eight output pins. (Ports P20-P23, D5-D7 are also used as segment output pins SEG16-SEG19, INT input pin, XCIN, and XCOUT, respectively). This section describes each port I/O function, related registers, application example using each port function and notes. 2.1.1 I/O ports (1) Port P0 Port P0 is a 4-bit I/O port. Port P0 has the key-on wakeup function and pull-up transistor. s Input/output of port P0 q Data input to port P0 Set the output latch of specified port P0i (i=0 to 3) to "1" with the OP0A instruction. If the output latch is set to "0," "L" level can be input. The state of port P0 is transferred to register A when the IAP0 instruction is executed. q Data output from port P0 The contents of register A is output to port P0 with the OP0A instruction. The output structure is an N-channel open-drain (built-in pull-up resistor). (2) Port P1 Port P1 is a 4-bit I/O port. Port P1 has the key-on wakeup function and pull-up transistor which turn ON/OFF by setting register PU0. s Input/output of port P1 q Data input to port P1 Set the output latch of specified port P1i (i=0 to 3) to "1" with the OP1A instruction. If the output latch is set to "0," "L" level can be input. The state of port P1 is transferred to register A when the IAP1 instruction is executed. q Data output from port P1 The contents of register A is output to port P1 with the OP1A instruction. The output structure is an N-channel open-drain. Note: When the pull-up function becomes valid, simultaneously, the key-on wakeup function becomes valid. Accordingly, be careful when using the key-on wakeup function. (Refer to the Table 2.1.1 and notes for the power down function.)
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APPLICATION
2.1 I/O pins
(3) Port P2 Port P2 is a 4-bit input port. s Input of port P2 Port P2 is also used as SEG16-SEG19. Accordingly, when ports P20/SEG16-P23/SEG19 are used as port P2, set the corresponding bits of the LCD control register L2 to "1." q Data input to port P2 The state of port P2 is transferred to register A when the IAP2 instruction is executed. (4) Port D D0-D7 are eight independent output ports. s Output of port D Each pin of port D has an independent 1-bit wide output function. For output of ports D0-D7, select one of port D with the register Y of the data pointer first. q Data output from port D Set the output level to the output latch with the SD and RD instructions. The state of pin enters the high-impedance state when the SD instruction is executed. The states of all port D enter the high-impedance state when the CLD instruction is executed. The state of pin becomes "L" level when the RD instruction is executed. The output structure is an N-channel open-drain. Notes 1: When the SD and RD instructions are used, do not set "10002" or more to register Y. 2: Port D6 is also used as XCIN, and port D7 is also used as XCOUT. Accordingly, when using port D6 and D7 functions, set the clock control register MR2 to "0."
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APPLICATION
2.1 I/O pins
2.1.2 Related registers (1) Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P10-P13 pull-up transistor and the ON/OFF of the keyon wakeup function. Set the contents of this register through register A with the TPU0A instruction. The contents of register PU0 is transferred to register A with the TAPU0 instruction. Table 2.1.1 shows the pull-up control register PU0. Table 2.1.1 Pull-up control register PU0 Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 at reset : 00002 0 1 0 1 0 1 0 at power down : state retained R/W
Pull-up transistor OFF, no key-on wakeup function Pull-up transistor ON, key-on wakeup function Pull-up transistor OFF, no key-on wakeup function Pull-up transistor ON, key-on wakeup function Pull-up transistor OFF, no key-on wakeup function Pull-up transistor ON, key-on wakeup function Pull-up transistor OFF, no key-on wakeup function Pull-up transistor ON, key-on wakeup function
pull-up transistor control bit 1 Note: "R" represents read enabled, "W" represents write enabled.
(2) LCD control register L2 Register L2 is used to select the port P2 function or segment output pin function. Set the contents of this register through register A with the TL2A instruction. Table 2.1.2 shows the LCD control register L2. Table 2.1.2 LCD control register L2 LCD control register L2 L23 L22 L21 L20 P23/SEG19 function switch bit P22/SEG18 function switch bit P21/SEG17 function switch bit P20/SEG16 function switch bit at reset : 11112 0 1 0 1 0 1 0 1 SEG19 P23 SEG18 P22 SEG17 P21 SEG16 P20 at power down : state retained W
Note: "W" represents write enabled.
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APPLICATION
2.1 I/O pins
(3) Clock control register MR The oscillation circuit control bit is assigned to the bit 2 of the clock control register MR. Set the contents of this register through register A with the TMRA instruction. The contents of register MR is transferred to register A with the TAMR instruction. Table 2.1.3 shows the clock control register MR. Table 2.1.3 Clock control register MR Clock control register MR at reset : 10002 0 1 MR0 = 0 MR0 = 1 MR0 = 0 MR0 = 1 f(XIN) f(XCIN) f(XIN)/4 f(XCIN)/4 at power down : state retained R/W
MR3
System clock (STCK) selection bit
MR2 MR1 MR0
f(XCIN) oscillation circuit control 0 1 bit 0 f(XIN) oscillation circuit control bit 1 Clock selection bit
(XCIN) oscillation stop, ports D6, D7 selected (XCIN) oscillation enabled, ports D6, D7 not selected Oscillation enabled Oscillation stop
0 f(XIN) 1 f(XCIN) Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When setting ports, MR3, MR1, MR0 are not used. 3: Do not stop the oscillation circuit selected with the clock selection bit (MR0). Note the stop of the oscillation circuit selected with the clock selection bit (MR0) if the following setting is performed. Example 1: (MR3MR2MR1MR0) = !0!1 (f(XCIN) selected, f(XCIN) oscillation stop) Example 2: (MR3MR2MR1MR0) = !!10 (f(XIN) selected, f(XIN) oscillation stop) !: "0" or "1."
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APPLICATION
2.1 I/O pins
2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor. Outline: The connecting required external part is just keys. Specifications: Port D is used to output "L" level and port P0 is used to input 16 keys. Multiple key inputs are not detected. Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing.
M34551
D0
SW4
SW3
SW2
SW1
SW8
SW7
SW6
SW5
D1
SW12 SW11 SW10 SW9
D2
SW16 SW15 SW14 SW13
D3
P00 P01 P02 P03
Fig. 2.1.1 Key input by key scan
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APPLICATION
2.1 I/O pins
Switch of key input selection port (D0D1) Waiting time for stabilizing until input Reading of port (key input)
Key input cycle High D0 Low High D1 Low High D2 Low High D3 Low IAP0 Input of SW1-SW4 IAP0 Input of SW5-SW8 IAP0 Input of SW9-SW12 IAP0 Input of SW13-SW16 IAP0
Input of SW1-SW4
Note: Output from port D is high-impedance state.
Fig. 2.1.2 Input timing of key scan
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APPLICATION
2.1 I/O pins
2.1.4 Notes on use (1) Note when an I/O port is used as an input port Set the output latch to "1" and input the port value before input. If the output latch is set to "0," "L" level can be input. (2) Noise and latch-up prevention Connect an approximate 0.1 F bypass capacitor directly to the VSS line and the VDD line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the One Time PROM version. Connect the CNVSS/VPP pin to VSS through an approximate 5 k resistor which is connected to the CNVSS/VPP pin at the shortest distance. (3) Note on multifunction Port D5 is also used as the INT pin. Note that the port D5 output function can be used even when INT pin function is selected. (4) Connection of unused pins Table 2.1.4 shows the connections of unused pins. (5) SD, RD instructions When the SD and RD instructions are used, do not set "10002" or more to register Y. Table 2.1.4 connections of unused pins Connection Pin Connect to VSS pin, or set the output latch to "0." D0-D4, D5/INT Select D6 and D7 and connect to VSS, or set the output latch to "0" and open. D6/XCIN, D7/XCOUT P20/SEG16-P23/SEG19 Select P2 and connect to VSS, or select segment output function and open. Open. CARR Open. SEG0-SEG15 Open. COM0-COM3 Set the output latch to "1" and open. P00-P03 Open or connect to VSS (Note). P10-P13 Note: In order to connect ports P10-P13 to VSS, turn off their pull-up transistors (Pull-up control register PU0i="0") by software. In order to make these pins open, turn on their pull-up transistors (register PU0i="1") by software, or turn off their pull-up transistors (register PU0i="0") and set the output latch to "0" (i = 0, 1, 2, or 3). Be sure to select the key-on wakeup function and the pull-up function with every one port. (Note in order to set the output latch to "0" and make pins open) * After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to "0" by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. * To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note in order to connect unused pins to VSS or VDD) * To avoid noise, connect the unused pins to VSS or VDD at the shortest distance using a thick wire.
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APPLICATION
2.2 Interrupts
2.2 Interrupts
The 4551 Group has three interrupt sources : external interrupt (INT), timer 1 interrupt and timer 2 interrupt. This section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 Interrupt functions (1) External interrupt (INT) The interrupt request occurs by the change of input level of INT pin. The interrupt valid waveform can be selected by the bit 2 of the interrupt control register I1. s External interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the external interrupt occurs, the interrupt processing is executed from address 0 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set to "0." (2) Timer 1 interrupt The interrupt request occurs by the timer 1 underflow. s Timer 1 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the timer 1 interrupt occurs, the interrupt processing is executed from address 4 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set to "0." (3) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. s Timer 2 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the timer 2 interrupt occurs, the interrupt processing is executed from address 6 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set to "0."
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APPLICATION
2.2 Interrupts
2.2.2 Related registers (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more instruction. (2) Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.2.1 shows the interrupt control register V1. Table 2.2.1 Interrupt control register V1 Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 at power down : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) 1 Note: "R" represents read enabled, and "W" represents write enabled. (3) Interrupt request flag The activated condition for each interrupt is examined. Each interrupt request flag is set to "1" when the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Each interrupt request flag is cleared to "0" when either; *an interrupt occurs, or *the next instruction is skipped with a skip instruction.
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APPLICATION
2.2 Interrupts
(4) Interrupt control register I1 The interrupt valid waveform for INT pin is assigned to the bit 2 of register I1. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.2.2 shows the interrupt control register I1. Table 2.2.2 Interrupt control register I1 Interrupt control register I1 I13 Not used at reset : 00002 0 1 0 1 0 1 0 at power down : state retained R/W
This bit has no function, but read/write is enabled. Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction) Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction) This bit has no function, but read/write is enabled.
I12
Interrupt valid waveform for INT pin selection bit(Note 2)
I11 I10
Not used Not used
This bit has no function, but read/write is enabled. 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: Depending on the input state of D5/INT pin, the external interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction.
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APPLICATION
2.2 Interrupts
2.2.3 Interrupt application examples (1) External interrupt The INT pin is used for external interrupts, of which valid waveforms can be chosen, which can recognize the change of both edges ("H""L" or "L""H"). Outline: An external interrupt can be used by dealing with the change of edge ("H""L" or "L""H") in both directions as a trigger. Specifications: An interrupt occurs by the change of an external signals edge ("H""L" or "L""H"). Figure 2.2.1 shows an operation example of an external interrupt, and Figure 2.2.2 shows a setting example of an external interrupt. (2) Timer 1 interrupt Constant period interrupts by a setting value to timer 1 can be used. Outline: The constant period interrupts by the timer 1 underflow signal can be used. Specifications: Prescaler and timer 1 divide the system clock frequency f(XIN) = 3.6 MHz, and the timer 1 interrupt occurs every 1 ms. Figure 2.2.3 shows a setting example of the timer 1 constant period interrupt. (3) Timer 2 interrupt Timer 2 is the fixed dividing frequency, and the constant period interrupts which the count source is divided by 213 or 2 14 can be used. Outline: The constant period interrupts by the timer 2 underflow signal can be used. Specifications: Timer 2 divides the sub-clock frequency f(XCIN) = 32.768 kHz, and the timer 2 interrupt occurs every 0.5 sec. Figure 2.2.4 shows a setting example of the timer 2 constant period interrupt.
INT valid waveform
Falling
"H"
Rising
Falling
Rising
Falling
Rising
D5/INT "L" "1" "0"
Setting of valid waveform by I12
"H" D5/INT I12 "L" "1" "0"
Interrupt occurs after setting the valid waveform to "falling." The valid waveform of the next interrupt is set to "rising." When the interrupt which valid waveform is set to "rising" occurs, the opposite of the above processing is performed.
Fig. 2.2.1 External interrupt operation example
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APPLICATION
2.2 Interrupts
Disable Interrupts
External interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction)
Interrupt control register V1
! ! ! 0 External interrupt occur disabled (TV1A instruction)
Set Port
Port used for external interrupt is set to input port. Port D5 output latch "1" Set to input (SD instruction)
Set Valid Waveform
Valid waveform of INT pin is selected.
b3 b0
Interrupt control register I1 ! 1 ! !
b3 b0
Rising waveform selected (TI1A instruction) Falling waveform selected (TI1A instruction)
Interrupt control register I1 ! 0 ! !
g Note when interrupt valid waveform is changed
When is executed, depending on the input state of INT pin, the interrupt request flag EXF0 may be set to "1." Accordingly, insert the NOP instruction after the TI1A instruction.
Clear Interrupt Request
External interrupt activated condition is cleared. External interrupt request flag EXF0 "0" Clear the external interrupt activated condition (SNZ0 instruction)
g Note when interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
Enable Interrupts
External interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 ! ! ! 1 Interrupt enable flag INTE "1"
External interrupt occur enabled (TV1A instruction) All interrupts enabled (EI instruction)
External interrupt execution started
"!" : it can be "0" or "1."
Fig. 2.2.2 External interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock.
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APPLICATION
2.2 Interrupts
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled ( DI instruction)
Interrupt control register V1 ! 0 ! ! Timer 1 interrupt occur disabled ( TV1A instruction)
Stop Timer Operation
Timer 1 operation is temporarily stopped.
b3 b0
Timer control register V1 ! ! ! 0
Timer 1 operation stop ( TW2A instruction)
Set Timer Value
Timer 1 count time is set. (The formula is shown VA below.)
b3 b0
Timer control register W1 1 0 0 0 Timer 1 reload register R1 "4A16"
Prescaler divided by 4 selected ( TW1A instruction) Timer count value 74 set ( T1AB instruction)
Clear Interrupt Request
The timer 1 interrupt activated condition is cleared. Clear the timer 1 interrupt activated condition Timer 1 interrupt request flag T1F "0" (SNZT1 instruction)
g Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer 1 Operation
The timer 1 operation which is temporarily stopped is restarted.
b3 b0
Timer control register W2 ! ! ! 1
Timer 1operation start ( TW2A instruction)
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 ! 1 ! ! Interrupt enable flag INTE "1"
Timer 1 interrupt occur enabled ( TV1A instruction) All interrupts enabled ( EI instruction)
Constant period interrupt execution started
VA The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1ms are set as follows: 1ms = (3.6 MHz) - 1! 4 ! 3 ! 4 ! System clock Instruction Prescaler clock dividing ratio (74 + 1) Timer 1 count value
"!" : it can be "0" or "1."
Fig. 2.2.3 Timer 1 constant period interrupt setting example 2-14
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APPLICATION
2.2 Interrupts
Disable Interrupts
Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) Timer 1 interrupt occur disabled (TV1A instruction)
Interrupt control register V1 0 ! ! !
Set Timer Value
Timer 2 count time is set. (Only when timer count value is 213 214, the formula is shown VA below.) or b3 b0 When timer count value = 213, 0 1 ! ! Timer count value 213 set (TW2A instruction) timer control register W2 b3 b0 When timer count value = 214, 14 timer control registerW2 ! 0 0 ! Timer count value 2 set (TW2A instruction)
Reset Timer Value and Set Count Source
Timer 2 counter is initialized. (Initialization is performed only by setting W23 from 0 to 1.)
b3 b0
Timer control register W2
This processing and setting timer value shown can be executed simultaneously.
0 !!! Timer 2 reset
b3 b0
Timer control register W2 Timer control register W2
1!!!
b3 b0
0!!!
Timer 2 count source is returned to XCIN. (TW2A instruction)
Clear Interrupt Request
The timer 2 interrupt activated condition is cleared. Clear the timer 2 interrupt activated condition g0 h Timer 2 interrupt request flag T2F "0" (SNZT2 instruction)
g Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 1 ! ! ! Interrupt enable flag INTE "1"
Timer 2 interrupt occur enabled (TV1A instruction) All interrupts enabled (EI instruction)
Constant period interrupt execution started
V A The timer 2 count value to make the interrupt occur every 0.5s is set as follows: 0.5s = (32.768kHz) ! 2 Sub-clock Timer 2 count value
-1 14
"!" : it can be "0" or "1."
Fig. 2.2.4 Timer 2 constant period interrupt setting example
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2.2 Interrupts
2.2.4 Notes on use (1) Setting of external interrupt valid waveform Depending on the input state of D5/INT pin, the external interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. (2) Multiple interrupts Multiple interrupts cannot be used in the 4551 Group. (3) Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to "0" (interrupt disable state). In order to enable the interrupt at the same time when system returns from the interrupt, write EI and RTI instructions continuously. (4) D5/INT pin The D5/INT pin need not be selected the external interrupt input INT function or the normal output port D5 function. However, the EXF0 flag is set to "1" when a valid waveform output from port D5 is input to INT pin even if it is used as an output port D5. (5) Power down instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
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2.3 Timers
2.3 Timers
The 4551 Group has an 8-bit timer with a reload register, a 4-bit timer and the 14-bit fixed dividing frequency timer which has the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 Timer functions (1) Timer 1 s Timer operation s Carrier wave output auto-control function (Refer to section "2.4 Carrier generating circuit" for details.) (2) Timer 2 s Timer operation (Timer 2 has the function to return from clock operation mode (POF instruction execution)) s Watchdog function Watchdog timer provides a method to reset the system when a program runs wild. When the WRST instruction is executed after system is released from reset, in this time, the watchdog timer starts operating. System reset is performed if the WRST instruction is not performed while timer 2 counts 2 13. (3) Timer LC s LCD frame clock generating 2.3.2 Related registers (1) Interrupt control register V1 The timer 1 interrupt enable bit is assigned to the bit 2, and the timer 2 interrupt enable bit is assigned to the bit 3. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.3.1 shows the interrupt control register V1. Table 2.3.1 Interrupt control register V1 Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 at power down : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When timer is used, V10 is not used.
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2.3 Timers
(2) Timer control register W1 The timer 1 count source selection bits are assigned to bits 0 and 1, and the prescaler dividing ratio selection bit is assigned to the bit 2, and the prescaler control bit is assigned to the bit 3. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. Table 2.3.2 shows the timer control register W1. Table 2.3.2 Timer control register W1 Timer control register W1 W13 W12 Prescaler control bit Prescaler dividing ratio selection bit at reset : 00002 0 1 0 at power down : 00002 R/W
Stop (prescaler state initialized) Operating Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 8 1 W11 W10 Count source W11 0 0 Prescaler output (ORCLK) Timer 1 count source selection 0 1 bits 1 0 Carrier output (CARRY) W10 1 1 Carrier output/2 (CARRY/2) Note: "R" represents read enabled, and "W" represents write enabled. (3) Timer control register W2 The timer 1 control bit is assigned to the bit 0, and timer 2 count value selection bits are assigned to bits 1 and 2, and the timer 1 control bit is assigned to the bit 3. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. Table 2.3.3 shows the timer control register W2. Table 2.3.3 Timer control register W2 Timer control register W2 W23 W22 Timer 2 count source selection bit at reset : 10002 0 1 W21 0 1 0 1 f(XCIN) Prescaler output (ORCLK) Count source Underflow occur every 214 count Underflow occur every 213 count Not available Not available Stop (timer 1 state retained) at power down : - - - 02 R/W
W21 W20
W22 0 Timer 2 count value selection bits 0 1 1 Timer 1 control bit
0
Operating 1 Note: "R" represents read enabled, and "W" represents write enabled. "-" represents state retained.
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2.3 Timers
(4) Timer control register W3 The timer LC control bit is assigned to the bit 0, and timer LC count source selection bit is assigned to the bit 1. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. Table 2.3.4 shows the timer control register W3. Table 2.3.4 Timer control register W3 Timer control register W3 W31 W30 Timer LC count source selection bit Timer LC control bit at reset : 002 0 1 0 1 at power down : state retained R/W
Bit 3 of timer 2 is output (timer 2 count source divided by 16) System clock (STCK) Stop (timer LC state retained) Operating
Note: "R" represents read enabled, and "W" represents write enabled.
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2.3 Timers
2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: The constant period by the timer 1 underflow signal can be measured. Specifications: Timer 1 and prescaler divides the system clock frequency f(XIN) = 3.6 MHz, and the timer 1 interrupt request occurs every 4 ms. Figure 2.3.2 shows the setting example of the constant period measurement. (2) Timer operation: constant period counter by timer 2 The constant period by the setting timer count value can be measured. Outline: The correct time can be measured and the clock which has high-accuracy can be set up by using a 32.768 kHz quartz-crystal oscillator. Specifications: Timer 2 divides the sub-clock frequency f(XCIN) = 32.768 kHz, and the timer 2 interrupt request occurs every 250 ms. Figure 2.3.3 shows the setting example of constant period counter by timer 2. (3) Watchdog timer Watchdog timer provides a method to reset the system when a program run-away occurs. In the 4551 Group, the bit 12 of timer 2 is used for the watchdog timer. Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at a certain cycle which consists of timer 2's 8191 counts or less. Outline: Execute the WRST instruction in timer 2's 8192 count at the normal operation. If program runs wild, the WRST instruction is never executed and system reset occurs. Specifications: System clock frequency f(XIN) = 3.6 MHz, sub-clock frequency f(XCIN) = 32.768 kHz are used, and program run-away is detected by executing the WRST instruction in 250 ms. Figure 2.3.1 shows the watchdog timer function, and Figure 2.3.4 shows the example of watchdog timer.
Timer 2 value WEF flag WDF flag
3FFF16 1FFF16 0000 16
"1" "0" "1" "0" "H"
Internal reset signal
"L"
WRST instruction execution
WRST instruction execution
System reset
Fig. 2.3.1 Watchdog timer function
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2.3 Timers
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled ( DI instruction) Timer 1 interrupt occur disabled ( TV1A instruction)
Interrupt control register V1 ! 0 ! !
Stop Timer Operation
Timer 1 operation is temporarily stopped.
b3 b0
Timer control register W2 ! ! ! 0
Timer 1 operation stop ( TW2A instruction)
Set Timer Value
Timer 1 count time is set. (The formula is shown VA below.)
b3 b0
Timer control register W1 1 1 0 0 Timer 1 reload register R1 "9516"
Prescaler divided by 8 selected ( TW1A instruction) Timer count value 149 set ( T1AB instruction)
Clear Interrupt Request
The timer 1 interrupt activated condition is cleared. g0 h Timer 1 interrupt request flag T1F "0" Clear the timer 1 interrupt activated condition (SNZT1 instruction)
g Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer 1 Operation
The timer 1 operation which is temporarily stopped is restarted.
b3 b0
Timer control register W2 ! ! ! 1
Timer 1 operation start ( TW2A instruction)
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 ! 1 ! ! Interrupt enable flag INTE "1"
Timer 1 interrupt occur enabled ( TV1A instruction) All interrupts enabled ( EI instruction)
Constant period interrupt execution started
VA The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 4ms are set as follows: 4ms = (3.6 MHz)
-1
!4!3
!
8
!
(149 + 1) Timer 1 count value
System clock
Instruction clock
Prescaler dividing ratio
"!" : it can be "0" or "1."
Fig. 2.3.2 Constant period measurement setting example
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2.3 Timers
Disable Interrupts
Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) Timer 2 interrupt occur disabled (TV1A instruction)
Interrupt control register V1 0 ! ! !
Set Timer Value
When timer count value = 2 , ! 0 1 ! timer control register W2 14 b3 b0 When timer count value = 2 , !0 0 ! timer control register W2
13 b3
b0
Timer 2 count time is set. (Only when timer count value is 2 or 2 , the formula is shown VA below.)
13
13
14
Timer count value 2 set (TW2A instruction) Timer count value 2 set (TW2A instruction)
14
Reset Timer Value and Set Count Source
Timer 2 counter is initialized. Initialization is performed only by setting W23 from 0 to 1.
b3 b0
Timer control register W2
This processing and setting timer value shown can be executed simultaneously.
0 !!! Timer 2 reset
b3 b0
Timer control register W2 Timer control register W2
1!!!
b3 b0
0!!!
Timer 2 count source is returned to XCIN.
Clear Interrupt Request
The timer 2 interrupt activated condition is cleared. Timer 2 interrupt request flag T2F "0" g0 Clear the timer 2 interrupt activated condition h (SNZT2 instruction)
g Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 1 ! ! ! Interrupt enable flag INTE "1"
Timer 2 interrupt occur enabled (TV1A instruction) All interrupts enabled (EI instruction)
Constant period interrupt execution started
V A The timer 2 count value to make the interrupt occur every 0.25s is set as follows:
0.25s = (32.768kH z) Sub-clock
-1
! 213 Timer 2 count value
"!" : it can be "0" or "1."
Fig. 2.3.3 Constant period counter by timer 2 setting example
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2.3 Timers
Set Timer 2 Count Source
Timer 2 countsource is set.
b3 b0
Timer control register W2 0 ! ! !
XCIN selected (TW2A instruction)
Activate Watchdog Timer
Watchdog timer is activated. Watchdog timer enable flag WEF "1" Watchdog timer enable flag WEF set (WRST instruction)
Main routine (every 20 ms) WDF Flag Reset
Watchdog timer flag WDF is reset. "0"
gh 0
Watchdog timer flag WDF cleared (WRST instruction)
Main routine execution
Repeat
Do not perform the interrupt processing for reset of watchdog timer flag WDF. Interrupt may keep operating even when a program runs wild.
When going into RAM back-up mode
* * * * * * WRST; EPOF; POF2 Oscillation (RAM back-up mode) stop
WDF flag cleared POF instruction enabled
In the RAM back-up mode, the value of WDF flag is initialized. However, when the WDF flag is "1," at the same time, a microcomputer may be reset. When the watchdog timer and RAM back-up mode are used, execute the WRST instruction before system enters into the RAM back-up mode in order to initialize the WDF flag. "!" : it can be "0" or "1."
Fig. 2.3.4 Watchdog timer setting example
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APPLICATION
2.3 Timers
2.3.4 Notes on use (1) Prescaler Stop the prescaler operation to change its frequency dividing ratio. (2) Count source * Stop timer 1 or timer LC counting to change its count source. * When timer 2 count source changes from f(XCIN) to ORCLK (W23 = "0" W23 = "1"), the count value of timer 2 is initialized. However, when timer 2 count source changes from ORCLK to f(XCIN) (W23 = "1" W23 = "0") or the same count source is set again (W23 = "0" W23 = "0" or W23 = "1" W23 = "1"), the count value of timer 2 is not initialized. (3) Timer 2 Timer 2 has the watchdog timer function (WDT). When timer 2 is used as the WDT, note that the processing to initialize the count value and the execution of the WRST instruction. (4) Reading the count value Stop the prescaler and then execute the TAB1 instruction to read timer 1 data. (5) Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
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2.4 Carrier generating circuit
2.4 Carrier generating circuit
The 4551 Group has a carrier generating circuit that generates the transfer waveform by dividing the system clock (STCK) for each remote control carrier wave. Also, the 4551 Group has the function to control the carrier wave output from port CARR by using timer 1. This section describes carrier functions, related registers, application examples using each carrier output and notes. 2.4.1 Carrier functions (1) Carrier wave output Carrier wave is selected by the carrier wave selection register C1. Carrier output is started with the STCR instruction, and carrier output is stopped with the SPCR instruction. (2) Carrier wave output auto-control function Timer 1 can auto-control the output enable/disable interval of port CARR carrier wave by setting register C2.
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2.4 Carrier generating circuit
2.4.2 Related registers (1) Carrier wave selection register C1 The output waveform of carrier wave is selected. Set the contents of this register through register A with the TC1A instruction. Figure 2.4.1 shows the relationship between register C1 and carrier wave.
Carrier wave selection register C1
Register C1 Setting value
C13 C12 C11 C10
STCR instruction
(at reset: 0 1 1 1 2, at power down: 0 1 1 1 2, W) Output waveform
SPCR instruction
Carrier wave Frequency Duty
0
0
0
0
"H" "L"
1/3
STCK/24
0
0
0
1
"H" "L"
1/2 1/4
STCK/16
0
0
1
0
"H" "L"
0
0
1
1
"H" "L"
1/2
STCK/2
0 0 1 0 1 0 1 1
1 1 1 1 1 1 1 0
0 0 0 1 1 1 1 0
0 1 1 0 0 1 1 0
"H" "L"
1/2
"H" "L"
No carrier wave
No available
"H" "L"
"L" fixed
"H" "L"
1/3
STCK/12
1
0
0
1
"H" "L"
1/2 1/4
STCK/8
1
0
1
0
"H" "L"
1
0
1
1
"H" "L"
1/2
STCK
1
1
0
0
"H" "L"
1/2
Note:"W" represents write enabled.
Fig. 2.4.1 Carrier wave selection register
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2.4 Carrier generating circuit
(2) Carrier wave output control register C2 The carrier wave output auto-control bit is assigned to the bit. Set the contents of this register through register A with the TC2A instruction. Table 2.4.1 shows the carrier wave output control register C2. Table 2.4.1 Carrier wave output control register C2 Carrier wave output control register C2 C20 Carrier wave output auto-control bit at reset : 02 0 1 at power down : 02 W
Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid
Note: "W" represents write enabled. (3) Carrier wave generating control flag CR Execute the SPCR instruction to set the carrier wave generating control flag CR to "0." Execute the STCR instruction to set the carrier wave generating control flag CR to "1." Table 2.4.2 shows the carrier wave generating control flag CR. Table 2.4.2 Carrier wave generating control flag CR Carrier wave generating control flag CR CR Carrier wave generation control at reset : 02 0 1 at power down : 02 W
Carrier wave generating stop (SPCR instruction) Carrier wave generating start (STCR instruction)
Note: "W" represents write enabled.
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2.4 Carrier generating circuit
2.4.3 Carrier wave output application examples (1) Remote control waveform output by carrier wave output auto-control function The carrier wave output auto-control function can be used to turn carrier wave ON/OFF automatically by counting carrier waveform. Outline: CARRY is selected as the timer 1 count source and port CARR can be controlled. Output of waveform can be controlled by the bit C20. OFF interval can be output. Specifications: The 37.9 kHz carrier wave is output from port CARR by using system clock frequency f(XIN) = 3.64 MHz. Also, the timer 1 interrupt occurs, and at the same time, setting the next output interval is performed. Figure 2.4.2 and Figure 2.4.3 show the setting example of carrier wave auto-control, Figure 2.4.4 shows the setting example of carrier wave output interval.
Disable Interrupts
Timer 1 interrupt is temporarily disabled.
b3 b0
Interrupt control register V1 ! 0 ! ! Timer 1 interrupt occur disabled (TV1A instruction)
Stop Timer Operation and Carrier Operation
Timer 1 operation and carrier operation is temporarily stopped.
b3 b0
Timer control register W2 ! ! ! 0 Carrier wave generation control flag CR "0"
Timer 1 operation stopped (TW2A instruction) Carrier wave generation stop (SPCR instruction)
Change of Count Source
Timer 1 count source is changed.
b3 b0
Timer control register W1 ! ! 1 0
Count source CARRY selected (TW1A instruction)
Set Timer Value
Timer 1 count time is set. (The formula is shown VA below.) Reload register R1 "1416" Timer count value 20 is set (T1AB instruction)
Set Carrier Generation Circuit
Carrier wave frequency and duty ratio are set. Carrier wave selectionr register C1
b3 b0
0000
Frequency STCK/24, duty ratio 1/3 selected (TC1A instruction)
Continue to Figure 2.4.3 on the next page.
Fig. 2.4.2 Carrier wave auto-control setting example 1
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2.4 Carrier generating circuit
From preceding Figure 2.4.2.
Set Carrier Wave Output Auto-control
Carrier wave output auto-control is set to be valid. Carrier wave output cotrol register C2 0 "1" Auto-control valid by timer 1 ( TC2A instruction)
Clear Interrupt Request
The timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0" Clear the timer 1 interrupt activated condition (SNZT1 instruction)
g Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer 1 Operation
The timer 1 operation which is temporarily stopped is restarted.(Timer is stopped because count source is not operating.)
b3 b0
Timer control register W2
! ! ! 1 Timer 1 operation start ( TW2A instruction)
Enable Interrupts
Timer 1 interrupt which is temporarily disabled is enabled.
b3 b0
Interrupt control register V1 ! 1 ! ! Timer 1 interrupt occur enabled ( TV1A instruction)
Start Carrier Output
Carrier output is started. (In this time, timer 1 operation is started simultaneously.) Carrier wave generating control flag CR "1" Carrier wave generating started ( STCR instruction)
Carrier output started
Setting the Next Output Waveform
11
Set Next Waveform Data
The next carrier output length is set to bit C2 0 and reload register R1.
Interrupt occurs
12
Set Next Waveform Data
The next carrier output length is set to bit C2 0 and reload register R1.
Interrupt occurs
12
repeated
Refer to Figure 2.4.4 for the detail of setting output data.
VA The carrier wave which duty ratio is 1/3 is output with a 3.64 MHz oscillator for the 0.55 ms. 8.77 s 37.9 kHz = 3.64 MHz ! 1/4 ! 1/24 26.3 s
System clock Carrier wave dividing ratio
0.55 ms = (37.9 kHz) ! (20+1) 0.55 ms
Carrier wave frequency Timer 1 count value
-1
"!" : it can be "0" or "1."
Fig. 2.4.3 Carrier wave auto-control setting example 2
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2.4 Carrier generating circuit
Timer 1 start w
Timer 1 underflow
a
Reload register R1
a a
a a
a a
a a
a a
a b
b c
c d
d a
a
a
aa
C20
Port CARR output
16a
v Carrier wave output start ( STCR)
8a
a
b
c
d
a
Initial value "a" is set to timer 1. The carrier wave output is started with the STCR instruction. C20 is set to "0" to continue the carrier wave output. After timer 1 underflow is counted to 15 times by software, C20 is set to "1." After CARR output is turned OFF by timer 1 underflow, C20 is set to "0." After timer 1 underflow is counted to 7 times by software, C20 is set to "1." The next CARR OFF interval "b" is set to reload register R1. The next CARR output interval "c" is set to reload register R1. The next CARR OFF interval "d" is set to reload register R1. The next CARR output interval "a" is set to reload register R1.
Fig. 2.4.4 Carrier wave output interval setting example
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2.4 Carrier generating circuit
(2) Carrier wave generating by software Carrier wave generating can be output by software count. Outline: The carrier wave generating circuit is set to "no carrier wave" and carrier wave is generated by software. Specifications: The 37.9 kHz carrier wave is generated by using main clock frequency f(XIN) = 3.64 MHz. Figure 2.4.5 shows the generating example of carrier wave by software.
Set Carrier Wave Output Auto-control
Carrier wave output auto-control is set to be invalid. Carrier wave output control register C20 "0" Auto-control by timer 1 invalid (TC2A instruction)
Set Carrier Generation Circuit
Carrier wave frequency and duty ratio is set. Carrier wave selection register C1 0 1 0 1 No carrier wave (TC1A instruction)
b3 b0
Start Carrier Output
Carrier output is started. 1.10 s 1 instruction (3.30s)
STCK
CARR output
8.79 s
17.58 s
Description instruction example
STCR NOP
NOP SPCR NOP
NOP
NOP
NOP
STCR NOP
NOP SPCR NOP
Fig. 2.4.5 Carrier wave by software generating example
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2.4 Carrier generating circuit
2.4.4 Notes on use (1) Note on the carrier generating circuit stop In order to stop the carrier wave which has the cycle longer than that of the instruction clock with the SPCR instruction, stop it at the point when the carrier wave outputs "L" level in the SPCR instruction execution cycle. If this condition is not satisfied, the last "H" output interval of carrier wave is shortened. (2) Notes when using the carrier wave output auto-control function q Execute the STCR instruction after setting the timer 1 and register C2 in order to start the carrier generating circuit operation. q Stop the timer 1 (W20="0") after stopping the carrier generating circuit (SPCR instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. q If the carrier wave output auto-control function is invalidated (C20="0") while the carrier wave output is auto-controlled, the output of port CARR retains the state when the auto-control is invalidated regardless of timer 1 underflow. This state can be terminated by timer 1 stop (W20="0"). When the carrier wave output auto-control function is validated (C20="1") again after it is invalidated (C20="0"), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur. q Use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output auto-control function is selected. If the ORCLK is used as the count source, a hazard wave may occur in port CARR output because ORCLK is not synchronized with the carrier wave. q When "no carrier wave" is selected with register C1 ((C13C12C11C10) = (0101), (1101)), the disable/enable of the carrier wave output cannot be controlled by the carrier wave output autocontrol function.
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APPLICATION
2.5 LCD function
2.5 LCD function
The 4551 Group has an LCD (Liquid Crystal Display) controller/driver. 4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. This section describes the LCD operation description, related registers, application examples using the LCD and notes. 2.5.1 Operation description (1) LCD duty and bias control Table 2.5.1 shows the duty and maximum number of displayed pixels. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. Also, when using segment pins are 19 or less, SEG16-SEG19 can be used as an I/O port with register L2. Table 2.5.1 Duty and maximum number of displayed pixels Maximum number Used COM pins Duty Bias of displayed pixels 1/2 1/2 1/3 1/3 1/4 1/3 Note: Leave COM0, COM1 (Note) COM0-COM2 (Note) COM0-COM3 (Note) 80 segments unused COM pins open. 40 segments 60 segments
(2) LCD drive timing The frequency (F) of the LCD clock generating the LCD drive timing and frame frequency are shown below. Figure 2.5.1 shows the structure of the LCD clock circuit. q When the prescaler output (ORCLK) is used for the timer 2 count source (W23 = "1") F = ORCLK ! 1 16 ! 1 ! LC + 1 1 2
q When f(XCIN) is used for the timer 2 count source (W23 = "0") F = f(XCIN) ! 1 16
!
1 1 ! LC + 1 2
The frame frequency for each display method can be obtained by the following formula. Frame frequency = F n (Hz) Frame period = n F (s)
[F: Frame frequency, 1/n: Duty]
Timer 2 W23 XCIN ORCLK
0 1
STCK 1/16
(Note 2) W30 W31 0
1 0 1
(Note 1)
Timer LC
1/2
LCD clock
Notes 1: Count source is stopped by clearing W30 to "0." 2: When the LCD function is used, set W31 to "0."
Fig. 2.5.1 LCD clock control circuit structure
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2.5 LCD function
(3) LCD display method The 4551 Group has the LCD RAM area for the LCD display. When "1" is written to a bit in the LCD RAM data, the display pixel which correspond to the bit automatically turns on. Figure 2.5.2 shows the LCD RAM map.
Z X Y 8 9 10 11 12 13 14 15 COM Note: Bit 3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM3 2 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM2
0 1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM1 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 3 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM3
1 1 2 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM2 1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM1 0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 3 SEG16 SEG17 SEG18 SEG19
2 2 1 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19
0 SEG16 SEG17 SEG18 SEG19
COM3 COM2 COM1 COM0
LCD display RAM is not assigned.
Fig. 2.5.2 LCD RAM map 2.5.2 Related registers (1) LCD control register L1 The LCD duty and bias selection bits are assigned to bits 0 and 1. The LCD on/off bit is assigned to the bit 2. Set the contents of this register through register A with the TL1A instruction. The TAL1 instruction can be used to transfer the contents of register L1 to register A. Table 2.5.2 shows the LCD control register L1. Table 2.5.2 LCD control register L1 LCD control register L1 L13 L12 L11 Not used LCD on/off bit at reset : 00002 0 1 0 at power down : state retained R/W
This bit has no function, but read/write is enabled. Off Duty Not available 1/2 1/2 1/3 1/3 Bias
On 1 L11 L10 0 0 1
0 1/3 1 1 1/4 Note: "R" represents read enabled, and "W" represents write enabled. L10
LCD duty and bias selection bits 0 1
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2.5 LCD function
(2) LCD control register L2 Port P2 function and segment pin function of pins P20/SEG16-P23/SEG19 can be switched by setting register L2. Set the contents of this register through register A with the TL2A instruction. Table 2.5.3 shows the LCD control register L2. Table 2.5.3 LCD control register L2 LCD control register L2 L23 L22 L21 L20 P23/SEG19 function switch bit P22/SEG18 function switch bit P21/SEG17 function switch bit P20/SEG16 function switch bit at reset : 11112 0 1 0 1 0 1 0 1 SEG19 P23 SEG18 P22 SEG17 P21 SEG16 P20 at power down : state retained W
Note: "W" represents write enabled. (3) Timer control register W3 The timer LC control bit is assigned to the bit 0, and the timer LC count source selection bit is assigned to the bit 1. When the LCD display function is used, set the bit 1 to "0." Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. Table 2.5.4 shows the timer control register W3. Table 2.5.4 Timer control register W3 Timer control register W3 W31 W30 Timer LC count source selection bit Timer LC control bit at reset : 002 0 1 0 at power down : state retained R/W
Bit 3 of timer 2 is output (timer 2 count source divided by 16) System clock (STCK) Stop (timer LC state retained) Operating
1 Note: "R" represents read enabled, "W" represents write enabled.
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2.5 LCD function
2.5.3 LCD application examples (1) LCD display LCD display function can be used to display 80 pixels (maximum 4 common ! 20 segment). Outline: LCD can be displayed easily by using the LCD display function. Specifications: 1/4 duty and 1/3 bias LCD is displayed by using LCD display panel example. Timer 2 is used for the LCD clock source, the sub-clock f(XCIN) = 32.768 kHz is used for the timer 2 clock source, and the frame frequency is set to 85 Hz. Figure 2.5.3 shows the LCD display panel example, Figure 2.5.4 shows the segment assignment example, Figure 2.5.5 shows the LCD RAM assignment example, and Table 2.5.5 shows the frame frequency.
Program Su. Mo. Tu. We. Th. Fr. Sa. weeks SP EP Start Stop BS A.M. P.M.
Fig. 2.5.3 LCD display panel example
Every
CH
Program Su. Mo. Tu. We. Th. Fr. Sa. weeks SP EP Start Stop BS A.M. P.M.

Fig. 2.5.4 Segment assignment example
Every
CH
Z X Y 8 9 10 11 12 13 14 15 COM Note: Bit 3 2
1 0 1 0 3 Start Stop
* *
a 2 1 0 3 We.
Every weeks
1 2
-g -g -g -g -g -g -g -g
-e -e -f -e -e -e -e -e
-d -d -d -d -d -d -d -d
-c -c -c -c -c -c -c -c
Unused
* *
Unused Unused Unused
-f -f -f -f -f -f -f -f
-b -b -b -b -b -b -b -b
-a -a -a -a -a -a -a -a
BS
2 Tu. Sa. CH P.M.
1 0 Mo. Su. Fr. Tu. EP SP A.M. Program
f e
g
b c
d
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 LCD display RAM is not assigned.
Fig. 2.5.5 LCD RAM assignment example
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2.5 LCD function
Initialization
Operate Timer 2
Timer 2 count source is set to f(XCIN). (Refer to section "2.3 Timer.")
Set SEG16-SEG19
P20/SEG16-P23/SEG19 are set to output.
b3 b0
LCD control register L2 0 0 0 0 SEG16-SEG19 selected (TL2A instruction)
Stop Timer LC
Timer LC operation is stopped.
b1 b0
Timer control register W3
! 0 Timer LC stopped (TW3A instruction)
Set Timer LC
Timer LC value is set. (The formula is shown VA below.) Timer LC reload register RLC Timer LC TLC "216" Timer count value 2 is set. (TLCA instruction)
Initialization of LCD Display RAM
LCD display RAM is initialized.
LCD display RAM Initial data is set.
Set LCD Display Method
LCD duty and bias are set.
LCD control register L1 ! ! 1 1 1/4 duty and 1/3 bias set. (TL1A instruction)
b3 b0
Set Timer LC Count Source
Timer LC count source is changed.
b1 b0
Timer control register W3
Count source is set to bit 3 of timer 2 . 0 1 Timer LC start (TW3A instruction)
Display LCD
LCD display function is set to be valid.b3
b0
LCD control register LC ! 1 ! ! LCD turned ON (TL1A instruction)
to normal program
Display changed by rewriting LCD display RAM
V A The timer LC count value when the frame frequency is set to 85.3 Hz is set as follows: 1 1 1 1 85.3 Hz = (32.768 kHz) ! ! ! ! 2 4 16 (2+1) Sub-clock Bit 3 of Timer Duty timer 2 LC ratio
"!" : it can be "0" or "1."
Fig. 2.5.6 Initial setting example
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2.5 LCD function
Table 2.5.5 Frame frequency LCD clock = XCIN: 32.768 kHz
LCD clock = ORCLK: 910 kHz/12 LCD clock = ORCLK: 910 kHz/24 or or = ORCLK:3.64 MHz/48 = ORCLK:3.64 MHz/96 LCD timer Duty Duty Duty LCD timer LCD timer 1/2 1/3 1/4 value 1/2 1/3 1/4 value 1/2 1/3 1/4 value 512 Hz 341 Hz 256 Hz 0 1185 Hz 790 Hz 592 Hz 0 592 Hz 395 Hz 296 Hz 0 256 Hz 170 Hz 128 Hz 1 592 Hz 395 Hz 296 Hz 1 296 Hz 197 Hz 148 Hz 1 171 Hz 114 Hz 85 Hz 2 395 Hz 263 Hz 197 Hz 2 197 Hz 132 Hz 99 Hz 2 128 Hz 85 Hz 64 Hz 3 296 Hz 197 Hz 148 Hz 3 148 Hz 99 Hz 74 Hz 3 102 Hz 68 Hz 51 Hz 4 237 Hz 158 Hz 118 Hz 4 118 Hz 79 Hz 59 Hz 4 85 Hz 57 Hz 43 Hz 5 197 Hz 132 Hz 99 Hz 5 99 Hz 66 Hz 49 Hz 5 73 Hz 49 Hz 37 Hz 6 169 Hz 113 Hz 85 Hz 6 85 Hz 56 Hz 42 Hz 6 64 Hz 42 Hz 32 Hz 7 148 Hz 99 Hz 74 Hz 7 74 Hz 49 Hz 37 Hz 7 57 Hz 38 Hz 28 Hz 8 131 Hz 88 Hz 66 Hz 8 66 Hz 44 Hz 33 Hz 8 51 Hz 34 Hz 27 Hz 9 118 Hz 79 Hz 59 Hz 9 59 Hz 39 Hz 30 Hz 9 47 Hz 31 Hz 23 Hz 10 108 Hz 72 Hz 54 Hz 10 54 Hz 36 Hz 27 Hz 10 43 Hz 28 Hz 21 Hz 11 99 Hz 66 Hz 49 Hz 11 49 Hz 33 Hz 25 Hz 11 39 Hz 26 Hz 20 Hz 12 91 Hz 61 Hz 46 Hz 12 46 Hz 30 Hz 23 Hz 12 37 Hz 24 Hz 18 Hz 13 85 Hz 56 Hz 42 Hz 13 42 Hz 28 Hz 21 Hz 13 34 Hz 23 Hz 17 Hz 14 79 Hz 53 Hz 39 Hz 14 39 Hz 26 Hz 20 Hz 14 32 Hz 21 Hz 16 Hz 15 74 Hz 49 Hz 37 Hz 15 37 Hz 25 Hz 18 Hz 15 Note: Values in the table shows the frame frequency (however, the values are rounded off to the decimal points). 2.5.4 Notes on use (1) Timer LC count source Stop each timer counting to change timer LC count source.
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2.6 Power down function
2.6 Power down function
The 4551 Group has the clock operation mode and RAM back-up mode for the power down function. The 4551 Group enters 12 kinds of state which includes the reset state to reduce the power dissipation. Figure 2.6.1 shows the state transition, and Figure 2.6.2 shows the oscillation stabilizing time. In this section, the clock control function, each power down function, related register and application example for the power down function are described.
Reset
POF execution
A E
POF2 execution
K
A,E
Return input 1
I
Clock operating mode
f(XIN):Stop f(XCIN):Stop
f(XIN):Oscillation f(XCIN):Stop System clock; f(XIN)/4 MR=(10002)
(Stabilizing time d )
MR3 1 MR3 0
(Note 2)
f(XIN):Oscillation f(XCIN):Stop System clock; f(XIN) MR=(00002)
(Stabilizing time d )
A,E
Return input 1
A,E
(Stabilizing time a )
A,E
(Stabilizing time a )
MR2 1
MR2 0
MR2 1
POF execution
B,F
Return input 1, 2
J
Clock operating mode
f(XIN):Stop f(XCIN) : Oscillation
B
f(X
1 2 1 MRR3 ime t M ing
( ab St iliz
MR2 0
M MRR2 2 0 1 (Note 2)
0 2 0 MRR3 M M MR R3 3 1 d )(S tab 0 i
liz ing tim e d)
F
IN):Oscillation
f(XCIN):Oscillation System clock; f(XIN)/4 MR=(11002) MR0 1 MR0 0
MR3 1 MR3 0
(Note 2)
f(XIN):Oscillation f(XCIN):Oscillation System clock; f(XIN) MR=(01002) MR0 1
RAM back-up mode
f(XIN):Stop f(XCIN):Stop
POF2 execution
B,F
Return input 1
B,F
(Stabilizing time a )
B,F
(Stabilizing time a )
POF execution
M 1 0 MRR0 R0 0 3 MR 0 1 M MR 1 0 MR 0 R3 M3 (Note 2) 3 1 MR 0
MR0 0
(Note 2)
C
G
POF2 execution
C,G
Return input 1, 2
f(XIN):Oscillation f(XCIN):Oscillation System clock; f(XCIN)/4 MR=(11012)
(Stabilizing time c )
MR3 1 MR3 0
f(XIN):Oscillation f(XCIN):Oscillation System clock; f(XCIN) MR=(01012)
(Stabilizing time c )
C,G
Return input 1
C,G
(Stabilizing time c ) (Note 1)
MR1 1
MR1 0
MR1 1
tim
e
POF execution
D,H
Return input 1, 2
1 1 MR 3 MR
1
c)
(St
ab
iliz
MR MR 1 3 1 0
MR1 0
M MR R1 (S 3 tab 0 iliz 1 ing
C,G
(Stabilizing time b )
0 1 0 MRR3 time M ing
c)
POF2 execution
D
H
D,H
(Stabilizing time c ) (Note 1)
f(XIN):Stop f(XCIN):Oscillation System clock; f(XCIN)/4 MR=(11112)
MR3 1 MR3 0
f(XIN):Stop f(XCIN):Oscillation System clock; f(XCIN) MR=(01112)
D,H
Return input 1
D,H
(Stabilizing time b )
Stabilizing time a : An interval required to stabilize the f(X IN) oscillation is automatically generated by hardware. Stabilizing time b : An interval required to stabilize the f(X CIN) oscillation is automatically generated by hardware. Stabilizing time c : Generate an interval required to stabilize the f(X IN) oscillation in state C or G by software at the transition D C, DG, HC, HG, JC, or JG. Stabilizing time d : Generate an interval required to stabilize the f(X CIN) oscillation in state B, F by software at the transition A B, EF, AF, or EB. Return input 1: External wakeup signal (P0 0-P03, P10-P13) Return input 2: Timer 2 interrupt request flag Notes 1. MR3="1"The microcomputer starts its operation after counting f(X CIN) clock signal 59 to 70 times. MR3="0"The microcomputer starts its operation after counting f(X CIN) clock signal 32 to 43 times. 2. When the following 2 conditions are satisfied, the transition A E, BF, AF, CF, GF represented by " " can be executed. (1) VDD = 2.2 V to 5.5 V (One Time PROM version: V DD = 2.5 V to 5.5 V), f(X IN) 1.0 MHz (2) VDD = 4.5 V to 5.5 V, f(X IN) 2.0 MHz
Fig. 2.6.1 State transition
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2.6 Power down function
q Oscillation stabilizing time a f(XIN) (Note) Oscillation condition satisfied
f(XIN) is counted 10757 to 10786 times. Software start (address 0 in page 0)
q Oscillation stabilizing time b
f(XCIN) (Note) Oscillation condition satisfied
f(XIN) is counted 10757 to 10786 times. Software start (address 0 in page 0)
q Oscillation stabilizing time c (software operating) f(XIN)
f(XCIN)
f(XIN) oscillation f(XIN) available stabilizing time is generated by software. Oscillation condition satisfied q Oscillation stabilizing time c (when returning from clock operating mode to state C, G) f(XIN)
f(XCIN)
MR3="1": f(XCIN) is counted 59 to 70 times. f(XIN) oscillation wait f(XIN) available MR3="0": f(XCIN) is counted 32 to 43 times. time by software Return input q Oscillation stabilizing time d Software start (address 0 in page 0)
f(XIN)
f(XCIN)
f(XCIN) oscillation f(XCIN) available stabilizing time is generated by software. Oscillation condition satisfied Note : Time until 4551 Group recognize oscillation. expresses system clock.
Fig. 2.6.2 Oscillation stabilizing time in each mode 2-40
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2.6 Power down function
2.6.1 Clock control function The 4551 Group can reduce the power dissipation by controlling oscillation with the clock control register MR. Refer to section "3.1 Electrical characteristics" for the oscillation frequency and power dissipation. In Figure 2.6.1, directions in which state transition can be executed are expressed by the arrow. For example, execute the transition A B ((XCIN) oscillation stabilizing wait) G H to execute the transition from the state A (MR3MR2MR1MR0 = 1000) after reset to the state H (MR3MR2MR1MR0 = 0111). Note: Do not stop the oscillation circuit selected by clock selection bit (MR0). Note the stop of the oscillation circuit selected with the clock selection bit (MR0) if the following setting is performed. Example 1: (MR3MR2MR1MR0) = (!0!1) (f(XCIN) selected, f(XCIN) oscillation stop) Example 2: (MR3MR2MR1MR0) = (!!10) (f(XIN) selected, f(XIN) oscillation stop) !: "0" or "1." 2.6.2 Power down function When the POF instruction or POF2 instruction is executed just after the EPOF instruction, system enters the power down state. Table 2.6.1 shows the internal state at each mode. Also, Table 2.6.2 shows the return source from this state. (1) Clock operating mode In this mode, current dissipation can be reduced by stopping XIN-XOUT oscillation and system clock with the states of RAM, reset circuit, XCIN-XCOUT oscillation, LCD display and timer 2 retained. (2) RAM back-up mode As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced without losing the contents of RAM.
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2.6 Power down function
Table 2.6.1 Functions and states retained at RAM back-up mode and the clock operating mode Clock operating Function RAM back-up Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Clock control register MR Timer control register W1 Timer control registers W2, W3 Interrupt control register V1 Interrupt control register I1 Carrier wave control registers and flag (C1, C2, CR) LCD display function LCD control registers L1, L2 Timer LC Timer 1 function Timer 2 function External 0 interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Watchdog timer flag (WDF) Watchdog timer enable flag (WEF) Interrupt enable flag (INTE) ! O O O ! O ! O ! O O O ! O ! ! O O O ! ! O O O ! O ! O ! (Note 3) O (Note 4) ! O ! ! O ! O !
General-purpose register V2 ! ! Notes 1: "O" represents that the function can be retained, and "!" represents that the function is initialized. Registers and flags other than the above are undefined at power down, and set an initial value after returning from power down state. 2: The stack pointer (SP) points the level of the stack register and is initialized to "1112" at power down. 3: LCD is turned off. 4: The state of timer is undefined.
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2.6 Power down function
Table 2.6.2 Return source and return condition Return source Ports P0, P1 Return condition Remarks Returns by an external falling Port P0 shares the falling edge detection circuit with edge input ("H""L"). port P1. The key-on wakeup function of port P0 is always valid. The only key-on wakeup function of the port P1 bit of which the pull-up transistor is turned on is valid. Set all the port using the key-on wakeup function to "H" level before going into the power down state.
External wakeup signal
Timer 2 interrupt Returns by timer 2 underflow The timer 2 interrupt request flag (T2F) can be used and setting T2F flag to "1." only when system returns from the clock operating mode request flag (POF instruction execution). However, if the POF and POF2 instructions are executed while the T2F flag = "1", its operation is recognized as the return condition and system returns from the clock operating mode. Note: P1 pin has the pull-up transistor which can be turned on/off by software. (3) Start condition identification When system returns from both power down and reset, software is started from address 0 in page 0. The start condition (warm start or cold start) can be identified by examining the state of the power down flag (P) with the SNZP instruction. Also, warm start condition (timer 2 or external wakeup signal) can be identified by the state of the T2F flag. Table 2.6.3 shows the start condition identification, and Figure 2.6.3 shows the start condition identified example. Table 2.6.3 Start condition identification Return condition P flag T2F flag External wakeup signal input 1 1 Timer 2 interrupt request flag 1 1 Reset 0 0
Software start P = "1" ? No Cold start Yes
Yes
T2F = "1" ? No
Return by timer 2 underflow
Return by external wakeup signal
Fig. 2.6.3 Start condition identified example
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2.6 Power down function
2.6.3 Related register (1) Clock control register MR Clock control register MR controls the system clock. Set the contents of this register through register A with the TMRA instruction. The TAMR instruction can be used to transfer the contents of register MR to register A. Table 2.6.4 shows the clock control register MR. Table 2.6.4 Clock control register MR Clock control register MR at reset : 10002 0 1 0 1 0 1 0 MR0=0 MR0=1 MR0=0 at power down : state retained f(XIN) f(XCIN) f(XIN)/4 R/W
MR3
System clock (STCK) selection bit f(XCIN) oscillation circuit control bit f(XIN) oscillation circuit control bit Clock selection bit
MR2 MR1 MR0
MR0=1 f(XCIN)/4 f(XCIN) oscillation stop, ports D6 and D7 selected f(XCIN) oscillation enabled, ports D6 and D7 not selected Oscillation enabled Oscillation stop f(XIN)
1 f(XCIN) Note: "R" represents read enabled, and "W" represents write enabled. (2) Pull-up control register PU0 Pull-up control register PU0 controls the pull-up function and key-on wakeup function. Set the contents of this register through register A with the TPU0A instruction. The TAPU0 instruction can be used to transfer the contents of register PU0 to register A. Table 2.6.5 shows the pull-up control register PU0. Table 2.6.5 Pull-up control register PU0 Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor at reset : 00002 0 1 0 1 0 1 0 at power down : state retained R/W
Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup Pull-up transistor ON, key-on wakeup Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup control bit 1 Note: "R" represents read enabled, and "W" represents write enabled.
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2.6 Power down function
2.6.4 Power down function application example (1) Clock display A clock which is high-accuracy and low-power dissipation can be set up by using a 32.768 kHz quartz-crystal as a sub-clock and executing the POF instruction. Outline: The power dissipation can be reduced by using the POF instruction. Specifications: Time is displayed by the LCD and a 32.768 kHz quartz-crystal oscillator. The main routine is executed by key input. Figure 2.6.4 shows the software setting example.
Software start Initialization of register Z Yes
Address 0 in page 0
P = "1" ? No
Cold start initial setting
Warm start initiai setting
T2F = "1" ? No
Yes
Clock counter + 1
Time display renewed
Key input ? Yes
No
Main routine initial setting
DI EPOF POF
To main routine
Fig. 2.6.4 Software setting example 2.6.5 Notes on use (1) Key-on wakeup function After setting ports (P1 specified with register PU0 and P0) which key-on wakeup function is valid to "H," execute the POF or POF2 instruction. "L" level is input to the falling edge detection circuit even if one of ports which key-on wakeup function is valid is in the "L" level state, and the edge is not detected. (2) Power down instruction Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the power down state. Note that system cannot enter the power down state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction. (3) POF2 instruction If the POF and POF2 instructions are executed while the T2F flag = "1," its operation is recognized as the return condition and system returns from power down state.
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2.7 Reset
2.7 Reset
System reset is performed by applying "L" level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied; q the value of supply voltage is the minimum value or more of the recommended operating conditions, q oscillation is stabilized. Then when "H" level is applied to the RESET pin, the software starts from address 0 in page 0 after elapsing the internal oscillation stabilizing time (f(XIN) is counted 10757 to 10786 machine cycles). Figure 2.7.3 shows the oscillation stabilizing time. 2.7.1 Reset circuit The 4551Group has the power-on reset circuit and voltage drop detection circuit. (1) Power-on reset Reset can be performed automatically at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time until the supply voltage rises to the minimum operation voltage to 100 s or less. When the rising time exceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, input "L" level to RESET pin until the supply voltage reaches the minimum operation voltage. Figure 2.7.1 shows the power-on reset example and Figure 2.7.2 shows the reset circuit example when the supply voltage rising time exceeds 100 s.
VDD
Pull-up transistor
RESET pin
Power-on reset circuit
Internal reset signal Reset state
Power-on reset circuit output voltage
Voltage drop detection circuit (Note)
Watchdog timer output WEF
Internal reset signal
Note:
This symbol represents a parasitic diode. Applied potential to RESET pin must Power-on be VDD or less.
Reset released
Fig. 2.7.1 Power-on reset circuit example
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2.7 Reset
Calculate the capacitor value to input "L" level until the supply voltage reaches the minimum operation voltage.
Pull-up transistor
RESET pin
Power-on reset circuit
Internal reset signal
Voltage drop detection circuit (Note)
Watchdog timer output WEF
Note:
This symbol represents a parasitic diode. Applied potential to RESET pin must be VDD or less.
Fig. 2.7.2 Reset circuit example when the supply voltage rising time exceeds 100 s
Reset input 1machine cycle or more
=
f(XIN) is counted 10757 to 10786 times
0.85VDD RESET 0.3VDD (Note)
Software start (Address 0 in page 0)
Note: Keep the value of supply voltage the minimum value or more of the recommended operating conditions.
Fig. 2.7.3 Oscillation stabilizing time after system is released from reset
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APPLICATION
2.7 Reset
2.7.2 Internal state at reset Figure 2.7.4 shows the internal state at reset. The contents of timers, registers, flags and RAM other than shown in Figure 2.7.4 are undefined, so set them to initial values.
* Program counter (PC) ............................................................................................ 000000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) ................................................................................... 0 * Power down flag (P) ............................................................................................... 0 * External 0 interrupt request flag (EXF0) ................................................................ 0 * Interrupt control register V1 ................................................................................... 0000 * Interrupt control register I1 .................................................................................... 0000 * Timer 1 interrupt request flag (T1F) ...................................................................... 0 * Timer 2 interrupt request flag (T2F) ...................................................................... 0 * Watchdog timer flag (WDF) ................................................................................... 0 * Watchdog timer enable flag (WEF) ....................................................................... 0 * Timer control register W1 ...................................................................................... 0000 * Timer control register W2 ...................................................................................... 0000 * Timer control register W3 ...................................................................................... 00 * Clock control register MR ...................................................................................... 1000 * Carrier wave selection register C1 ........................................................................ 0111 * Carrier wave output control register C2 ................................................................. 0 * Carrier wave generating control flag CR ............................................................... 0 * LCD control register L1 .......................................................................................... 0000 * LCD control register L2 .......................................................................................... 1111 * Pull-up control register PU0 ................................................................................... 0000 * General-purpose register V2 ................................................................................. 0000 * Carry flag (CY) ....................................................................................................... 0 * Register A .............................................................................................................. 0000 * Register B .............................................................................................................. 0000 * Register D .............................................................................................................. !!! * Register E .............................................................................................................. !!!!!!!! * Data pointer X ........................................................................................................ 0000 * Data pointer Y ........................................................................................................ 0000 * Data pointer Z ........................................................................................................ !! * Stack pointer (SP) .................................................................................................. 111 "!" represents undefined. (Carrier wave output disabled) (LCD off) (Port P2 selected) (Prescaler stopped) (Timer 1 stopped) (Timer LC stopped) (Interrupt disabled) 0 0 0 0 0 0 0 0
(Interrupt disabled)
Fig. 2.7.4 Internal state at reset
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APPLICATION
2.7 Reset
2.7.3 Voltage drop detection circuit The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Figure 2.7.5 shows the voltage drop detection reset circuit, and Figure 2.7.6 shows the operation waveform example of the voltage drop detection circuit.
Pull-up transistor
RESET pin
Power-on reset circuit
Internal reset signal
Voltage drop detection circuit
Watchdog timer output
WEF
Fig. 2.7.5 Voltage drop detection reset circuit
VDD
Reset voltage (Note)
The microcomputer starts operation after the f(XIN) is counted 10757 to 10786 times.
Internal reset signal
Note: Refer to section "3.1 Electrical characteristics" for the reset voltage of the voltage drop detection circuit.
Fig. 2.7.6 Voltage drop detection circuit operation waveform
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APPLICATION
2.8 Oscillation circuit
2.8 Oscillation circuit
The 4551 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The clock signal f(XIN) is obtained by connecting a ceramic resonator to XIN pin and XOUT pin. The clock signal f(XCIN) is obtained by connecting a quartz-crystal oscillator to X CIN pin and XCOUT pin. 2.8.1 Oscillation circuit (1) f(XIN) clock generating circuit The clock signal f(XIN) is obtained by connecting a ceramic resonator externally. Connect this external circuit to pins XIN and XOUT at the shortest distance. A feed-back resistor is built-in between XIN pin and XOUT pin. Figure 2.8.1 shows an example of an oscillation circuit connecting a ceramic resonator externally. Keep the maximum value of oscillation frequency within the range listed Table 2.8.1. (2) f(XCIN) clock generating circuit The clock signal f(XCIN) is obtained by connecting a quartz-crystal externally. Connect this external circuit to pins XCIN and XCOUT at the shortest distance. A feed-back resistor is built-in between XCIN pin and XCOUT pin. Figure 2.8.2 shows an example of an oscillation circuit connecting a quartz-crystal externally. Table 2.8.1 Maximum value of oscillation frequency and supply voltage Supply voltage 4.5 V to 5.5 V 4.5 V to 5.5 V 2.2 V to 5.5 V (Note) 2.5 V to 5.5 V (Note) (System clock) (f(XIN)/4) (f(XIN)) (f(XIN)/4) Oscillation frequency 8.0 MHz 2.0 MHz 4.0 MHz
(f(XIN)) 1.0 MHz Note: 2.5 V to 5.5 V for the One Timer PROM version.
M34551
XIN
CIN
Note: Externally connect a damping resistor Rd depending on the oscillaXOUT tion frequency. (A feedback resistor is built-in.) Rd Use the resonator manufacturer's recommended value because COUT constants such as capacitance depend on the resonator.
M34551 XCIN
CIN
Note: Externally connect a damping resistor Rd depending on the oscillaXCOUT tion frequency. (A feedback resistor is built-in.) Rd Use the quartz-crystal oscillator manufacturer's recommended value beCOUT cause constants such as capacitance depend on the oscillator.
Fig. 2.8.1 Oscillation circuit example connecting ceramic resonator externally
Fig. 2.8.2 Oscillation circuit example connecting quartz-crystal externally
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APPLICATION
2.8 Oscillation circuit
2.8.2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation. For the 4551 Group, the clock (f(XIN)), (f(XIN)/4), (f(XCIN)), or (f(XCIN))/4 which is supplied from the oscillation circuit is selected with the register MR. Figure 2.8.3 shows the structure of the clock control circuit.
MR0
XIN XOUT
OSC
Multiplexer
Frequency dividing circuit (divided by 4)
MR3
Internal clock 1 0 generating circuit (divided by 3)
INSTCK
STCK
XCIN XCOUT
POF instruction R S POF2 instruction R S Q Q
MR1
OSC
RESET T2F flag
Falling detected
Ports P0, P1
Fig. 2.8.3 Structure of clock control circuit 2.8.3 Notes on use (1) Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. Accordingly, consult the oscillator manufacturer for values of each part connected the oscillator.
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APPLICATION
2.8 Oscillation circuit
MEMO
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CHAPTER 3 APPENDIX
3.1 Electrical characteristics 3.2 Typical characteristics 3.3 List of precautions 3.4 Notes on noise 3.5 Mask ROM confirmation form 3.6 ROM programming confirmation form 3.7 Mark specification form 3.8 Package outline
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings
Symbol VDD VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, RESET, XIN, XCIN Output voltage P0, P1, D Output voltage CARR, XOUT, XCOUT Output voltage SEG, COM Power dissipation Operating temperature range Storage temperature range Output transistors in cut-off state Conditions Ratings -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 -20 to 70 -40 to 125 Unit V V V V V mW C C
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APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions
(Mask ROM version:Ta = -20 C to 70 C, VDD = 2.2 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 70 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter Conditions f(XIN) 4.0 MHz, ceramic resonator, Mask ROM version STCK=f(XIN)/4 f(XIN) 1.0 MHz, ceramic resonator, STCK=f(XIN) f(XIN) 4.0 MHz, ceramic resonator, VDD STCK=f(XIN)/4 Supply voltage One Time PROM version f(XIN) 1.0 MHz, ceramic resonator, STCK=f(XIN) f(XIN) 8.0 MHz, ceramic resonator, STCK=f(XIN)/4 f(XIN) 2.0 MHz, ceramic resonator, VRAM VSS VIH VIH VIH VIH VIL VIL VIL RAM back-up voltage Supply voltage "H" level input voltage P0, P1, P2 "H" level input voltage XIN "H" level input voltage RESET "H" level input voltage INT "L" level input voltage P0, P1, P2 "L" level input voltage XIN "L" level input voltage RESET VDD=5.0 V VDD=3.0 V VDD=5.0 V VDD=3.0 V VDD=5.0 V VDD=3.0 V VDD=5.0 V VDD=3.0 V Quartz-crystal oscillator Mask ROM version One Time PROM version TPON 1.15 1.30 1.00 1.50 1.65 STCK=f(XIN) RAM back-up 2.5 5.5 V 2.2 5.5 Limits Min. Typ. Max. Unit
4.5
5.5
2.0 0 0.8VDD 0.7VDD 0.85VDD 0.8VDD 0 0 0 0
5.5 VDD VDD VDD VDD 0.3VDD 0.3VDD 0.3VDD 0.2VDD 10 4 5 2 -30 -15 -15 -7 50 2.15 2.00 2.00 1.85 100
V V V V V V V V V V mA mA mA mA kHz
"L" level input voltage INT VIL IOL(peak) "L" level peak output current P0, P1, D0-D7, CARR IOL(avg) "L" level average output current P0, P1, D0-D7, CARR (Note) IOH(peak) "H" level peak output current CARR IOH(avg) "H" level average output current CARR (Note) f(XCIN) VDET f(XCIN) clock frequency Voltage drop detection circuit
V
1.15 VDD = 0 to 2.2 V Valid power supply rising time for Mask ROM version One Time PROM version VDD = 0 to 2.5 V power-on reset circuit Note: The average output current is the average current value at the 100 ms interval.
s
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APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics Table 3.1.3 Electrical characteristics
(Mask ROM version:Ta = -20 C to 70 C, VDD = 2.2 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = -20 C to 70 C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol VOL VOH IIH IIL IOZ Parameter "L" level output voltage P0, P1, D0-D7, CARR, RESET "H" level output voltage CARR "H" level input current P0, P1, P2, RESET "L" level input current P1, P2 Output current at off-state D0-D7 IOL = 5 mA IOL = 2 mA IOH = -15 mA IOH = -7 mA VI = VDD (Note 1) VI = 0 V (Note 1) VO = VDD VDD = 5.0 V, f(XCIN) = 32 kHz, f(XIN) = 8 MHz STCK = f(XIN)/4 VDD = 5.0 V at active high-speed mode while LCD is operating (SEG0-SEG15) f(XCIN) = 32 kHz f(XIN) = 1 MHz STCK = f(XIN) VDD = 3.0 V, f(XCIN) = 32 kHz, f(XIN) = 4 MHz STCK = f(XIN)/4 VDD = 3.0 V f(XCIN) = 32 kHz STCK = f(XIN) IDD Supply current (Note 2) at active low-speed mode while LCD is operating (SEG0-SEG15) VDD = 5.0 V f(XIN) = stop f(XCIN) = 32 kHz VDD = 3.0 V f(XIN) = stop f(XCIN) = 32 kHz at clock operating mode while LCD is operating (SEG0-SEG15) at RAM back-up mode P0, P1 RPH Pull-up resistor RESET value INT VT+ - VT- Hysteresis
RESET
Test conditions VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V
Limits Min. Typ. Max. 0.9 0.9 2.4 1.0 1 -1 1 2.5 5.0 4.6 2.8
Unit V V
A A A
f(XIN) = 2 MHz
2.3 1.4 0.7
mA 1.4 1.2 0.8 140 180
f(XIN) = 1 MHz f(XIN) = 500 kHz STCK = f(XCIN)/4 STCK = f(XCIN) STCK = f(XCIN)/4 STCK = f(XCIN) VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V
0.6 0.4 70 90 30 40 27.5 10
A
60 80 60 17.5 65 20 0.1 20 40 12 25 50 100 30 60 0.5 0.4 1.5 0.6 1.3 1.6 1.8 2.2 6.5 8 9 11 1.0 10 125 250 70 130
f(XIN) = stop f(XCIN) = 32 kHz Ta=25 C f(XIN) = stop f(XCIN) = 32 kHz
A
VDD = 3.0 V f(XIN) = stop, f(XCIN) = stop, Ta = 25 C
f(XIN) = stop, f(XCIN) = stop VDD = 5.0 V, VI = 0 V VDD = 3.0 V, VI = 0 V VDD = 5.0 V, VI = 0 V VDD = 3.0 V, VI = 0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Impedance between VLC3 and VSS
A
k k V V k k
RCOM RSEG RVLC
COM output impedance SEG output impedance LCD power supply internal resistor value
600 1200 k 300 Ta=25 C (Note 3) Notes 1: In this case, the pull-up transistor of port P1 is turned off and the port P2 function is selected by software. 2: The current value includes the current dissipation of the LCD power supply internal resistor (RVLC). 3: VLC3=VDD.
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APPENDIX
3.1 Electrical characteristics
3.1.4 Basic timing diagram
Machine cycle
Mi Parameter System clock Port D output
Pin name
Mi+1
STCK D0-D7
Ports P0, P1 output
P00-P03 P10-P13
Ports P0, P1 and P2 input
P00-P03 P10-P13 P20-P23
Interrupt input
INT
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APPENDIX
3.2 Typical characteristics
3.2 Typical characteristics
3.2.1 VDD-IDD characteristics (1) CPU high-speed operating (system clock: f(XIN)) [measurement condition] XIN: operating, XCIN: 32 kHz, timer 2 count source: XCIN, system clock: f(XIN), LCD clock: 1 kHz, duty: 1/4, bias: 1/3 Ta = 25C 5.0
4.5
4.0
3.5
IDD (mA)
3.0
f(XIN) = 2 MHz
2.5
2.0
f(XIN) = 1 MHz
1.5
f(XIN) = 500 kHz
1.0 0.5
0.0 0 1 2 3 4 5 6 7
VDD (V) (2) CPU high-speed operating (system clock: f(XIN)/4) [measurement condition] XIN: operating, XCIN: 32 kHz, timer 2 count source: XCIN, system clock: f(XIN)/4, LCD clock: 1 kHz, duty: 1/4, bias: 1/3 Ta = 25C 5.0
4.5
4.0
3.5
f(XIN) = 8 MHz
3.0
IDD (mA)
2.5
f(XIN) = 4 MHz
2.0 1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
VDD (V) 3-6
4551 Group User's Manual
APPENDIX
3.2 Typical characteristics
(3) CPU low-speed operating (system clock: f(XCIN)) [measurement condition] XIN: stop, XCIN: 32 kHz, timer 2 count source: XCIN, system clock: f(XCIN), LCD clock: 1 kHz, duty: 1/4, bias: 1/3 Ta = 25 C
150
100
IDD (A)
50 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
VDD (V) (4) CPU low-speed operating (system clock: f(XCIN)/4) [measurement condition] XIN: stop, XCIN: 32 kHz, timer 2 count source: XCIN, system clock: f(XCIN)/4, LCD clock: 1 kHz, duty: 1/4, bias: 1/3 Ta = 25 C
150
100
IDD (A)
50 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
VDD (V)
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APPENDIX
3.2 Typical characteristics
(5) Clock operating [measurement condition] XIN: stop, XCIN: 32 kHz, timer 2 count source: XCIN, system clock: stop, LCD clock: 1 kHz, duty: 1/4, bias: 1/3 Ta = 25 C
100
80
IDD (A)
60
40
20
0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
VDD (V)
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APPENDIX
3.2 Typical characteristics
3.2.2 VOH-IOH characteristics (port CARR) (1) VDD = 3.0 V
-50.0 -45.0 -40.0 -35.0
Ta = 25 C
IOH (mA)
-30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
VOH (V)
(2) VDD = 5.0 V
Ta = 25 C
-100.0 -90.0 -80.0 -70.0
IOH (mA)
-60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (V)
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APPENDIX
3.2 Typical characteristics
3.2.3 VOL-IOL characteristics (Ports P0, P1, D0-D7, CARR, RESET) (1) VDD = 3.0 V
50.0 45.0 40.0 35.0
Ta = 25 C
IOL (mA)
30.0 25.0 20.0 15.0 10.0 5.0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
VOL (V)
(2) VDD = 5.0 V
Ta = 25 C
100.0 90.0 80.0 70.0
IOL (mA)
60.0 50.0 40.0 30.0 20.0 10.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL (V)
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APPENDIX
3.2 Typical characteristics
3.2.4 Voltage drop detection circuit temperature characteristics (1) M34551Mx-XXXFP
2.5
Supply voltage (V)
2
1.5
1 -20 -10 0 10 20 30 40 50 60 70
Operating temperature range (C) (2) M34551E8-XXXFP
2.5
Supply voltage (V)
2
1.5
1 -20 -10 0 10 20 30 40 50 60 70
Operating temperature range (C)
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APPENDIX
3.3 List of precautions
3.3 List of precautions
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use the thickest wire. In the built-in PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k (connect this resistor to CNVSS/ VPP pin as close as possible). * Use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier wave output autocontrol function is selected. If the ORCLK is used as the count source, a hazard may occur in port CARR output because ORCLK is not synchronized with the carrier wave. * When "no carrier wave" is selected with register C1 ((C13C12C11C10) = (0101), (1101)), the enable/disable of the carrier wave output cannot be controlled by the carrier wave output auto-control function.
D5/INT pin
When the interrupt valid waveform of D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Clear the bit 0 of register V1 to "0" and then change the interrupt valid waveform of D5/INT pin with the bit 2 of register I1 (refer to Figure 40). * Clear the bit 2 of register I1 to "0" and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 40). Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. . . . LA TV1A LA TI1A NOP SNZ0 NOP . . . 4 ; Change of the interrupt valid waveform
Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
Count source
Stop timer 1 or timer LC counting to change its count source. When timer 2 count source changes from f(XCIN) to ORCLK (W23 = "0" W23 = "1"), the count value of timer 2 is initialized. However, when timer 2 count source changes from ORCLK to f(XCIN) (W23 = "1" W23 = "0") or the same count source is set again (W23 = "0" W23 = "0" or W23 = "1" W23 = "1"), the count value of timer 2 is not initialized.
Timer 2
Timer 2 has the watchdog timer function (WDT). When timer 2 is used as the WDT, note that the processing to initialize the count value and the execution of the WRST instruction.
4
; (!!!02) ; The SNZ0 instruction is valid
Reading the count value
Stop the prescaler and then execute the TAB1 instruction to read timer 1 data.
;The SNZ0 instruction is executed ! : this bit is not related to the setting of INT.
Writing to reload register R1
Write the data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
Notes when using the carrier wave output auto-control function
* Execute the STCR instruction after setting the timer 1 and register C2 in order to start the carrier generating circuit operation. * Stop the timer 1 (W20="0") after stopping the carrier generating circuit (SPCR instruction executed) while the carrier wave output is disabled in order to stop the carrier wave output auto-control operation. * If the carrier wave output auto-control function is invalidated (C20="0") while the carrier wave output is auto-controlled, the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This state is released by timer 1 stop (W20="0"). When the carrier wave output auto-control function is validated (C20="1") again after it is invalidated (C20="0"), the auto-control of carrier wave output is started again when the next timer 1 underflow occurs. However, when the carrier wave output auto-control bit is changed during timer 1 underflow, the error-operation may occur.
Fig. 40 External 0 interrupt program example
One Time PROM version
The operating power voltage of the One Time PROM version is within the range of 2.5 V to 5.5 V.
Multifunction
Note that the port D5 output function can be used even when INT function is selected.
11
Power down instruction (POF instruction, POF2 instruction) Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the power down state. Note that system cannot enter the power down state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instrcution. counter Make sure that the PCH does not specify after the last page of the built-in ROM.
12 Program
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APPENDIX
3.4 Notes on noise
3.4 Notes on noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Package Select the smallest possible package to make the total wiring length short. q Reason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise.
(2) Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the VSS pin with the shortest possible wiring (within 20mm). q Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
N.G.
RESET VSS
DIP SDIP SOP QFP
O.K.
Reset circuit VSS
RESET VSS
Fig. 3.4.2 Wiring for the RESET input pin Fig. 3.4.1 Selection of packages
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APPENDIX
3.4 Notes on noise
(3) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. (4) Wiring to CNVSS pin Connect the CNVSS pin to the VSS pin with the shortest possible wiring. q Reason The processor mode of a microcomputer is influenced by a potential at the CNVSS pin. If a potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
Noise
XIN XOUT VSS
N.G.
XIN XOUT VSS
O.K.
CNVSS VSS
CNVSS VSS
Fig. 3.4.3 Wiring for clock I/O pins q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
N.G.
O.K.
Fig. 3.4.4 Wiring for CNVSS pin
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APPENDIX
3.4 Notes on noise
(5) Wiring to VPP pin of One Time PROM version q When the VPP pin is also used as the CNVSS pin Connect an approximately 5 k resistor to the VPP pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible (refer to Figure 3.4.5) Note: Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the microcomputer operates correctly. q Reason The VPP pin of the One Time PROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway.
When the VPP pin is also used as the CNVSS pin Approximately 5k CNVSS/VPP VSS
3.4.2 Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin.
VCC
VCC
VSS
VSS
N.G.
O.K.
Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line
In the shortest distance
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version
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APPENDIX
3.4 Notes on noise
3.4.3 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance.
N.G.
Do not cross
CNTR XIN XOUT VSS
Fig. 3.4.8 Wiring to a signal line where potential levels change frequently (3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the underside of a printed circuit board
Microcomputer Mutual inductance M Large current GND XIN XOUT VSS
Oscillator wiring pattern example
Fig. 3.4.7 Wiring for a large current signal line (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the CARR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
XIN XOUT VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 VSS pattern on the underside of an oscillator
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4551 Group User's Manual
APPENDIX
3.4 Notes on noise
3.4.4 Setup for I/O ports Setup I/O ports using hardware and software as follows: * Connect a resistor of 100 or more to an I/O port in series. * As for an input port, read data several times by a program for checking whether input levels are equal or not. * As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. * Rewrite data to pull-up control registers at fixed periods. 3.4.5 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. * Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine) initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. * Decrements the SWDT contents by 1 at each interrupt processing. * Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). * Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less.
Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing >0 RTI Return Main routine errors
Main routine (SWDT) N EI Main processing N (SWDT) =N? N
(SWDT) 0? 0
Interrupt processing routine errors
Fig. 3.4.10 Watchdog timer by software
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. * Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. * Detects that the interrupt processing routine has failed and determines to branch to the program
4551 Group User's Manual
3-17
APPENDIX
3.5 Mask ROM order confirmation form
3.5 Mask ROM order confirmation form
GZZ-SH10-66B <63A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34551M4-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V. Mask ROM number Date: Receipt ) 000016 4.00K 0FFF16 400016 4.00K 4FFF16 FFFF16
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
V1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation)
EPROM Type:
27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
000016 4.00K 0FFF16 400016 4.00K 4FFF16 7FFF16
High-order 5-bit data
432109876543210987654321 1 432109876543210987654321 43210987654321098765432 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
5432109876543210987654321 1 5432109876543210987654321 543210987654321098765432 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (48P6S-A for M34551M4-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
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4551 Group User's Manual
Issuance signature
Responsible Supervisor officer
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-94B <85A0> 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34551M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V.
Mask ROM number Date: Receipt ) 000016 8.00K 1FFF16 400016 8.00K 5FFF16 FFFF16
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL (
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation)
EPROM Type:
27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16
High-order 5-bit data
432109876543210987654321 1 432109876543210987654321 43210987654321098765432 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
5432109876543210987654321 1 5432109876543210987654321 543210987654321098765432 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321 5432109876543210987654321
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (48P6S-A for M34551M4-XXXFP) and attach to the Mask ROM Order Confirmation Form. V 3. Comments
4551 Group User's Manual
Issuance signature
Responsible Supervisor officer
3-19
APPENDIX
3.6 ROM programming order confirmation form
3.6 ROM programming order confirmation form
GZZ-SH10-69B <64A0> 4500 SERIES ROM PROGRAMMING ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34551E8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked V. ROM number Date: Receipt
Issuance signature
Section head S u p e r v i s o r signature signature
Company name V Customer Date issued Date: TEL ( )
Responsible Supervisor officer
V 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation)
EPROM Type:
27C256
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
27C512
Low-order 5-bit data
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
000016 8.00K 1FFF16 400016 8.00K 5FFF16 7FFF16
000016 8.00K 1FFF16 400016 8.00K 5FFF16 FFFF16
High-order 5-bit data
432109876543210987654321 1 43210987654321098765432 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
High-order 5-bit data
432109876543210987654321 1 43210987654321098765432 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
Set "FF16" in the shaded area. Set "1112" in the area of low-order and high-order 5-bit data. V 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (48P6S-A for M34551E8-XXXFP) and attach to the ROM Programming Order Confirmation Form. V 3. Comments
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APPENDIX
3.7 Mark specification form
3.7 Mark specification form
48P6S-A (48-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
38
25
39
24
Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit)
48 15
1
14
B. Customer's Parts Number + Mitsubishi IC Catalog Name
38
25
39
24
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's parts number can be up to 9 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, (c), . (periods), , (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required
Mitsubishi lot number (6-digit or 7-digit)
48 15
1
14
C. Special Mark Required
38
25
39
24
Notes1 : If Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated technically as close as possible. Mitsubishi lot number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the cunstomer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special logo required
48
15
1
14
4551 Group User's Manual
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APPENDIX
3.8 Package outline
3.8 Package outline
48P6S-A
EIAJ Package Code QFP48-P-710-0.65 HD D
48 39
Plastic 48pin 7!10mm body QFP
JEDEC Code - Weight(g) 0.29 Lead Material Alloy 42
e
MD
1
38
b2
I2 Recommended Mount Pad
HE E
Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME
14
25
15
24
A L1
e y
b
F
A1
Detail F
L
Dimension in Millimeters Min Nom Max - - 2.15 0.1 0.2 0 1.85 - - 0.2 0.25 0.35 0.13 0.15 0.2 6.8 7.0 7.2 9.8 10.0 10.2 0.65 - - 8.7 9.0 9.3 11.7 12.0 12.3 0.3 0.5 0.7 1.0 - - 0.1 - - 0 10 - - - 0.35 1.0 - - - - 7.4 - - 10.4
A2
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4551 Group User's Manual
c
ME
MITSUBISHI SEMICONDUCTORS USER'S MANUAL 4551 Group
Sep. First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
(c)1998 MITSUBISHI ELECTRIC CORPORATION
User's Manual 4551 Group
MITSUBISHI ELECTRIC CORPORATION
HEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYO
(c) 1998 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Jul. 1997. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition Revision Description
4551 Group User's Manual
Rev. date 980930
(1/1)

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